Digital to analog converter with precise linear output for both positive and negative digital input values

Abstract

A circuit and method for converting a digital number to an analog output signal, wherein the most significant bit or "sign" bit of the digital number is used for switching the accumulated currents of the other data bits to a chain of operational amplifiers employing feedback resistors for conversion into an output voltage of magnitude and sign corresponding to the input digital number. A decoding circuit and method enables the circuit to present an output voltage corresponding to the two's--complement of the input digital number.

I claim: 
     
       1. A circuit for converting a digital number having positive or negative sign to an analog output signal, comprising: transistor switches for producing weighted currents representing bits that have a predetermined state for combination into a sum current;   operating amplifiers serially connected in a unity-gain configuration, each operational amplifier having feedback resistors for obtaining a precise output voltage, for converting said sum current into a voltage with a polarity with respect to a reference voltage corresponding to the signal of said digital number; and   switching circuitry for selectively delivering the sum current to a selected input of said operational amplifiers depending on the sign of the digital number for the purpose of determining the polarity with respect to said reference voltage of the analog output signal.   
     
     
       2. The circuit of claim 1 wherein the feedback resistors have substantially equal resistance values. 
     
     
       3. The circuit of claim 2 wherein said feedback resistors have precisely the same resistance values. 
     
     
       4. The circuit of claim 1 wherein said transistor switches for producing weighted bit currents comprises a decoder circuit for providing a two's-complement decoded value for negative input digital values to said switching circuitry. 
     
     
       5. The circuit of claim 4 further comprising a termination for unused bit currents. 
     
     
       6. A circuit for converting a digital number having a plurality of bits including a sign bit to an analog output signal having positive and negative voltage values with respect to a reference voltage, comprising: a weighting circuit for ascribing weighted currents to the bits of the digital number that have a predetermined state, and for developing sum currents comprising a sum of said weighted currents;   a first operational amplifier having inverting and non-inverting inputs and an output, and having a reference potential applied to said non-inverting input;   a first resistor connected between said inverting input and said output for providing feedback to said first operational amplifier;   a second operational amplifier having inverting and non-inverting inputs and an output, said inverting input connected to receive a signal from said output of said first operational amplifier, and having said reference potential applied to said non-inverting input;   a second resistor coupling the output of said first operational amplifier to the inverting input of the second operational amplifier;   a third resistor having a resistance value substantially equal to the resistance value of said first resistor connected between the output of said second operational amplifier and the inverting input of said second operational amplifier for providing feedback; and   a switch, controlled by said sign bit, for switching said sum currents when the sign bit is a first logical state to the inverting input of said second operational amplifier to produce a voltage at the output of said second operational amplifier that is positive with respect to said reference potential, and for switching said sum currents when the sign bit is a second logical state to the inverting input of said first operational amplifier to produce a voltage at the output of said second operational amplifier that is negative with respect to said reference potential.   
     
     
       7. The circuit of claim 6 wherein the sign bit is the most significant bit in the digital number. 
     
     
       8. The circuit of claim 6 wherein the first logical state is a logical "1" and the second logical state is a logical "0". 
     
     
       9. The circuit of claim 6 wherein said weighting circuit comprises a decoder circuit for providing a two's-complement decoded value for input digital values to the switch for switching sum currents. 
     
     
       10. The circuit of claim 6 further comprising a termination for unused bit currents. 
     
     
       11. The circuits of claim 9 wherein said first, second and third resistors have precisely equal resistance values. 
     
     
       12. A method for converting a digital number having a plurality of bits including a sign bit to an analog output signal having positive and negative voltage values with respect to a reference, comprising: providing a weighting circuit for ascribing weighted currents to the bits of the digital number that have a predetermined state, and for developing sum currents comprising a sum of said weighted currents;   providing a first operational amplifier having inverting and noninverting inputs and an output, and having a reference potential applied to said noninverting input;   providing a first resistor connected between said inverting input and said output for providing feedback to said first operational amplifier;   providing a second operational amplifier having inverting and noninverting inputs and an output, said inverting input connected to receive a signal from said output of said first operational amplifier, and having said reference potential applied to said noninverting input;   providing a second resistor for coupling the output of said first operational amplifier to the inverting input of the second operational amplifier;   providing a third resistor having a resistance value substantially equal to the resistance value of said first resistor connected between the output of said second operational amplifier and the inverting input of said second operational amplifier for providing feedback; and   providing a switch, controlled by said sign bit, for switching said sum currents when the signal bit is a first logical state to the inverting input of said second operational amplifier to produce a voltage at the output of said second operational amplifier that is positive with respect to said reference potential, and for switching said sum currents when the signal bit is a second logical state to the inverting input of said first operational amplifier to produce a voltage at the output of said second operational amplifier that is negative with respect to said reference potential.   
     
     
       13. The method of claim 12 wherein the sign bit is the most significant bit in the digital number. 
     
     
       14. The method of claim 12 wherein the first logical state is a logical "1" and the second logical state is a logical "0". 
     
     
       15. The method of claim 12 wherein said weighting circuit comprises a decoder circuit for providing a two's-complement decoded value for input digital values. 
     
     
       16. The method of claim 12 further comprising providing a termination for unused bit currents. 
     
     
       17. The method of claim 12 wherein said first resistor and said third resistor have precisely equal resistance values. 
     
     
       18. A method for converting a digital number having a positive or negative sign to an analog output signal, comprising the steps of: producing weighted bit currents representing the bits of the digital number for combination into a sum current;   selectively delivering said sum current to a selected input of a converting circuit depending on said sign of said digital number; and   converting said sum current into an output voltage by using said converting circuit, using operational amplifiers serially connected, having feedback resistors for obtaining a precise output voltage, in a transresistance configuration, said output voltage having a polarity which is based on a reference voltage, said output voltage forming the analog output signal.   
     
     
       19. The method of claim 18 wherein transistor switches are used for producing the weighted bit currents. 
     
     
       20. The method of claim 18 wherein said step of converting the sum current uses feedback resistors of substantially equal resistance values. 
     
     
       21. The method of claim 18 wherein said step of converting the sum current uses resistors of precisely equal values. 
     
     
       22. The method of claim 18 wherein the step of producing weighted bit currents comprises the step of generating a two's-complement decoded value for negative input digital values. 
     
     
       23. The method of claim 18 further comprising the step of providing a termination for unused bit currents.