Flash erasable single poly EPROM device

Abstract

A single polysilicon layer electrically programmable and electrically erasable read only memory cell is described. The cell utilizes an n-well inversion capacitor, formed in a semiconductor substrate as the control gate. One plate of the capacitor is formed from the same polysilicon layer as the floating gate of the memory device, thus capacitively coupling the floating gate and the inversion capacitor control gate. Additional erase performance is achieved by addition of a dedicated erase capacitor to the basic cell. Still further improvement in programming performance and protection against over-erase failure in a flash type EEPROM device is achieved by the addition of a select transistor. Prevention of program disturb and DC erase is also described.

What is claimed is: 
     
       1. An electrically programmable and electrically erasable floating gate memory device formed on a semiconductor substrate of a first conductivity type comprising: a first region of a second conductivity type;   a second region of said second conductivity type;   a channel region between said first and said second region;   a gate dielectric disposed above said channel region;   a gate disposed above said gate dielectric; and   a first capacitor, said first capacitor comprising a doped well of said second conductivity type and a plate capacitively coupled to said doped well, said plate being electrically coupled to said gate, wherein said memory device comprises means for electrically programming said memory device and means for electrically erasing said memory device, wherein said means for electrically programming comprise means for applying a first potential to said doped well and means for applying a second potential to said second region, and wherein said means for electrically erasing comprise means for applying a third potential to said first region.   
     
     
       2. The memory device as described in claim 1 wherein said first conductivity type is p and said second conductivity type is n. 
     
     
       3. The memory device as described in claim 2 wherein said doped well comprises a first diffusion region, said first diffusion region being heavily doped with a dopant of said second conductivity type, and a second diffusion region, said second diffusion region being heavily doped with a dopant of said first conductivity type, wherein electrical contact is made to said doped well through means for making electrical contact coupled to said first and said second diffusion regions. 
     
     
       4. The memory device as described in claim 2 wherein said gate and said plate comprise a single, continuous polysilicon layer. 
     
     
       5. The memory device as described in claim 3 wherein said gate and said plate comprise a single, continuous polysilicon layer. 
     
     
       6. An electrically programmable and electrically erasable floating gate memory device formed on a semiconductor substrate of a first conductivity type comprising: a first region of a second conductivity type;   a second region of said second conductivity type;   a channel region between said first and said second region;   a gate dielectric disposed above said channel region;   a gate disposed above said gate dielectric;   a first capacitor, said first capacitor comprising a first doped well of said second conductivity type and a first plate capacitively coupled to said first doped well, said first plate being electrically coupled to said gate; and   a second capacitor, said second capacitor comprising a second doped well of said second conductivity type and a second plate capacitively coupled to said second doped well, said second plate being electrically coupled to said gate, said memory device comprising means for electrically programming said memory device and means for electrically erasing said memory device.   
     
     
       7. The device as described in claim 6 wherein said first conductivity type is p and said second conductivity type is n. 
     
     
       8. The memory device as described in claim 7 wherein said first doped well comprises a first and a second diffusion region and said second doped well comprises a third and a fourth diffusion region, said first and said third diffusion regions being of said second conductivity type and said second and said fourth diffusion regions being of said first conductivity type, wherein electrical contact is made to said first doped well through said first and said second diffusion regions and electrical contact is made to said second doped well through said third and said fourth diffusion regions. 
     
     
       9. The memory device as described in claim 7 wherein said means for electrically programming comprise means for applying a first potential to said first doped well and a second potential to said second region, and wherein said means for electrically erasing comprise means for applying a third potential to said second doped well. 
     
     
       10. The memory device as described in claim 8 wherein said means for electrically programming comprise means for applying a first potential to said first doped well and a second potential to said second region, and wherein said means for electrically erasing comprise means for applying a third potential to said second doped well. 
     
     
       11. The memory device as described in claim 7 wherein said gate, said first plate and said second plate comprise a single, continuous polysilicon member. 
     
     
       12. The memory device as described in claim 8 wherein said gate, said first plate and said second plate comprise a single, continuous polysilicon member. 
     
     
       13. The memory device as described in claim 10 wherein said gate, said first plate and said second plate comprise a single, continuous polysilicon member. 
     
     
       14. The memory device as described in claim 11 wherein at least a portion of said second plate is heavily doped n-type. 
     
     
       15. The memory device as described in claim 12 wherein at least a portion of said second plate is heavily doped n-type. 
     
     
       16. The memory device as described in claim 13 wherein at least a portion of said second plate is heavily doped n-type. 
     
     
       17. The memory device as described in claim 14 wherein said third and said fourth diffusion regions are located adjacent to one another, and wherein at least a portion of said third and said fourth regions are located adjacent to said second plate. 
     
     
       18. An electrically programmable and electrically erasable floating gate memory device formed on a semiconductor substrate of a first conductivity type comprising: a first region of a second conductivity type;   a second region of said second conductivity type;   a first channel region between said first and said second region;   a gate dielectric disposed above said first channel region;   a first gate disposed above said gate dielectric;   a first capacitor, said first capacitor comprising a first doped well of said second conductivity type and a first plate capacitively coupled to said first doped well, said first plate being electrically coupled to said first gate;   a second capacitor, said second capacitor comprising a second doped well of said second conductivity type and a second plate capacitively coupled to said second doped well, said second plate being electrically coupled to said first gate; and   a select transistor comprising a second gate disposed on a second gate oxide, a third region of said second conductivity type, and a second channel region disposed beneath said third gate oxide and between said third region and said first region.   
     
     
       19. The device as described in claim 18 wherein said first conductivity type is p and said second conductivity type is n. 
     
     
       20. The memory device as described in claim 19 wherein said first doped well comprises a first and a second diffusion region and said second doped well comprises a third and a fourth diffusion region, said first and said third diffusion regions being of said second conductivity type and said second and said fourth diffusion regions being of said first conductivity type, wherein electrical contact is made to said first doped well through said first and said second diffusion regions and electrical contact is made to said second doped well through said third and said fourth diffusion regions. 
     
     
       21. The memory device as described in claim 19 wherein said device comprises means for electrically programming said memory device, said means for electrically programming comprising means for applying a first potential to said first doped well and a second potential to said second region, and wherein said device comprises means for electrically erasing said memory device, said means for electrically erasing comprising means for applying a third potential to said second doped well. 
     
     
       22. The memory device as described in claim 20 wherein said device comprises means for electrically programming said memory device, said means for electrically programming comprising means for applying a first potential to said first doped well and a second potential to said second region, and wherein said device comprises means for electrically erasing said memory device, said means for electrically erasing comprising means for applying a third potential to said second doped well. 
     
     
       23. The memory device as described in claim 19 wherein said first gate, said first plate and said second plate comprise a single, continuous polysilicon member. 
     
     
       24. The memory device as described in claim 20 wherein said first gate, said first plate and said second plate comprise a single, continuous polysilicon member. 
     
     
       25. The memory device as described in claim 22 wherein said first gate, said first plate and said second plate comprise a single, continuous polysilicon member. 
     
     
       26. The memory device as described in claim 23 wherein at least a portion of said second plate is heavily doped n-type. 
     
     
       27. The memory device as described in claim 24 wherein at least a portion of said second plate is heavily doped n-type. 
     
     
       28. The memory device as described in claim 25 wherein at least a portion of said second plate is heavily doped n-type. 
     
     
       29. The memory device as described in claim 26 wherein said third and said fourth diffusion regions are located adjacent to one another, and wherein at least a portion of said third and said fourth regions are located adjacent to said second plate. 
     
     
       30. An array of electrically programmable and electrically erasable floating gate memory devices formed on a semiconductor substrate of a first conductivity type, each of said devices comprising: a first region of a second conductivity type;   a second region of said second conductivity type;   a first channel region between said first and said second region;   a gate dielectric disposed above said first channel region;   a first gate disposed above said gate dielectric;   a first capacitor, said first capacitor comprising a first doped well of said second conductivity type and a first plate capacitively coupled to said first doped well, said first plate being electrically coupled to said first gate;   a second capacitor, said second capacitor comprising a second doped well of said second conductivity type and a second plate capacitively coupled to said second doped well, said second plate being electrically coupled to said first gate; and   a select transistor comprising a second gate disposed on a second gate oxide, a third region of said second conducitivity type, and a second channel region disposed beneath said third gate oxide and between said third region and said first region.   
     
     
       31. The array as described in claim 30 wherein said array comprises a device to be programmed, wherein said array comprises means for electrically programming said device to be programmed, said means for electrically programming comprising means for applying a first potential to said first doped well and a second potential to said second region of said device to be programmed. 
     
     
       32. The array as described in claim 31 wherein said array is arranged in a plurality of columns and rows of said devices, wherein one of said first regions and one of said second regions extend along each of said columns, wherein said one of said first regions and said one of said second regions is common to each of said devices in each of said columns, wherein said second gate and said first well are electrically coupled in parallel to each of said devices in each of said rows, wherein said device to be programmed is located in one of said rows and one of said columns, and wherein said means for electrically programming said device to be programmed further comprises means for turning on said select transistor in said row of said device to be programmed, and means for turning off said select transistor and means for applying a fourth potential to said first doped well in all other rows than said row of said device to be programmed. 
     
     
       33. The array as described in claim 31 wherein said array is arranged in a plurality of columns and rows of said devices, wherein one of said first regions and one of said second regions extend along each of said columns, wherein said one of said first regions and said one of said second regions is common to each of said devices in each of said columns, wherein said second gate and said first well are electrically coupled in parallel to each of said devices in each of said rows, and wherein said device to be programmed is located in one of said rows and one of said columns, and wherein said means for electrically programming further comprises means for grounding said first region in said column of said device to be programmed and means for allowing said first region to float in all other columns, and means for applying a fifth potential to said second region in all columns other than said column of said device to be programmed. 
     
     
       34. The memory device as described in claim 18 further comprising means for reading said memory device, said means for reading comprising means for applying a first potential to said first doped well, means for applying a second potential to said second gate, and means for sensing a current between said first region and said second region. 
     
     
       35. The array as described in claim 32 wherein said means for electrically programming further comprises means for grounding said first region in said column of said device to be programmed and means for allowing said first region to float in all other columns, and means for applying a fifth potential to said second region in all columns other than said column of said device to be programmed. 
     
     
       36. The memory device as described in claim 30 wherein said array comprises a device to be read, wherein said array is arranged in a plurality of columns and rows of said devices, wherein one of said first regions and one of said second regions extend along each of said columns, wherein said one of said first regions and said one of said second regions is common to each of said devices in each of said columns, wherein said second gate and said first well are electrically coupled in parallel to each of said devices in each of said rows, wherein said device to be read is located in one of said rows and one of said columns, and wherein said array comprises means for reading comprising means for applying a sixth potential to said first doped well in said row of said device to be read, means for turning on said select transistor in said row of said device to be read, means for turning off said select transistor in all other rows, and means for sensing a current between said first region and said second region of said column of said device to be read. 
     
     
       37. The memory device as described in claim 32 wherein said array comprises a device to be read, wherein said device to be read is located in one of said rows and one of said columns, and wherein said array comprises means for reading comprising means for applying a sixth potential to said first doped well in said row of said device to be read, means for turning on said select transistor in said row of said device to be read, means for turning off said select transistor in all other rows, and means for sensing a current between said first region and said second region of said column of said device to be read. 
     
     
       38. The memory device as described in claim 33 wherein said array comprises a device to be read, wherein said device to be read is located in one of said rows and one of said columns, and wherein said array comprises means for reading comprising means for applying a sixth potential to said first doped well in said row of said device to be read, means for turning on said select transistor in said row of said device to be read, means for turning off said select transistor in all other rows, and means for sensing a current between said first region and said second region of said column of said device to be read. 
     
     
       39. The array as described in claim 30 wherein said first conductivity type is p and said second conductivity type is n and wherein said first gate, said first plate and said second plate comprise a single, continuous polysilicon member. 
     
     
       40. The array as described in claim 32 wherein said first conductivity type is p and said second conductivity type is n and wherein said first gate, said first plate and said second plate comprise a single, continuous polysilicon member. 
     
     
       41. The array as described in claim 33 wherein said first conductivity type is p and said second conductivity type is n and wherein said first gate, said first plate and said second plate comprise a single, continuous polysilicon member. 
     
     
       42. The array as described in claim 36 wherein said first conductivity type is p and said second conductivity type is n and wherein said first gate, said first plate and said second plate comprise a single, continuous polysilicon member. 
     
     
       43. The array as described in claim 30 comprising a device to be erased and comprising means for electrically erasing said device to be erased, said means for electrically erasing comprising means for applying a third potential to said second doped well of said device to be erased. 
     
     
       44. The array as described in claim 32 comprising a device to be erased and comprising means for electrically erasing said device to be erased, said means for electrically erasing comprising means for applying a third potential to said second doped well of said device to be erased. 
     
     
       45. The array as described in claim 33 comprising a device to be erased and comprising means for electrically erasing said device to be erased, said means for electrically erasing comprising means for applying a third potential to said second doped well of said device to be erased. 
     
     
       46. The array as described in claim 35 comprising a device to be erased and comprising means for electrically erasing said device to be erased, said means for electrically erasing comprising means for applying a third potential to said second doped well of said device to be erased.