Method of making high mobility integrated drivers for active matrix displays

Abstract

High mobility thin film transistors for fabricating integrated drivers for active matrix displays and a special method of fabrication for obtaining the thin film transistors having mobility sufficiently high enough as drivers operable in the several megahertz frequency range needed for driving high resolution active matrix displays.

I claim: 
     
       1. A method for fabricating high mobility thin film transistors as integrated drivers on a substrate, comprising: growing a silicon dioxide layer on a silicon substrate;   etching the silicon dioxide layer to obtain a plurability of gate dielectric regions of silicon dioxide;   growing a epitaxial silicon layer on the silicon substrate and the gate dielectric regions;   depositing a barrier layer on the epitaxial silicon layer;   depositing a first light shield layer on the barrier layer;   bonding a glass substrate to the first light shield layer;   etching away the silicon substrate;   etching a portion of the epitaxial silicon layer and of the gate dielectric regions to form a plurability of islands situated on the glass substrate, wherein each island has the epitaxial silicon layer incorporating at least one gate dielectric region, the barrier layer and the first light shield layer;   coating a glass layer on the islands and exposed portions of the glass substrate on the same surface on which the islands are situated;   etching portions of the glass layer to expose at least the gate dielectric regions of each of the islands;   depositing a polysilicon layer on each gate dielectric region of each island;   etching a portion of the polysilicon layer and forming a polysilicon gate situated on each gate dielectric region;   implanting source and drain implantations into the exposed barrier layer on each island, at a thickness greater than the thickness of the gate dielectric region;   annealing the source and drain implantations;   depositing a silicon dioxide intermetal dielectric layer on the plurability of the islands and on remaining portions of the layer of glass;   etching contact vias through the silicon dioxide intermetal dielectric layer to the source and drain implantations on each island; and   depositing and etching source and drain metalizations to the source and drain implantations via the contact vias.   
     
     
       2. Method of claim 1 further comprising: depositing a silicon passivation dielectric layer on the source and drain metalizations;   depositing a second light shield layer on the silicon passivation dielectric layer; and   etching the second light shield layer to leave a portion of the second light shield layer over each island.   
     
     
       3. Method of claim 2 wherein: the silicon dioxide layer has a thickness between 0.01 and 1.0 micron;   the epitaxial silicon layer has a thickness between 0.01 and 5 microns;   the barrier layer has a thickness between 0.1 and 2 microns; and   the first light shield layer has a thickness between 0.01 and 2 microns.   
     
     
       4. A method for fabricating high mobility thin film transistors as integrated drivers on a substrate, comprising: growing a silicon dioxide layer on a silicon substrate;   etching the silicon dioxide layer to obtain a plurability of gate dielectric regions of silicon dioxide;   growing a epitaxial silicon layer on the silicon substrate and the gate dielectric regions;   depositing a barrier layer on the epitaxial silicon layer;   depositing a first light shield layer on the barrier layer;   bonding a glass substrate to the first light shield barrier;   etching away the silicon substrate;   etching a portion of the epitaxial silicon layer and of the gate dielectric regions to form a plurability of islands situated on the glass substrate, wherein each island has the epitaxial silicon layer incorporating at least one gate dielectric region, the barrier layer and the first light shield layer;   coating a glass layer on the islands and exposed portions of the glass substrate on the same surface on which the islands are situated;   etching portions of the glass layer to expose at least the gate dielectric regions of each of the islands;   depositing a polysilicon layer on each gate dielectric region of each island;   etching a portion of the polysilicon layer and forming a polysilicon gate situated on each gate dielectric region;   implanting source and drain implantations into the exposed barrier layer on each island, at a thickness greater than the thickness of the gate dielectric region;   annealing the source and drain implantations;   depositing a silicon dioxide intermetal dielectric layer on the plurability of the islands and on remaining portions of the layer of glass;   etching contact vias through the silicon dioxide intermetal dielectric layer to the source and drain implantations on each island; and   depositing and etching source and drain metalizations to the source and drain implantations via the contact vias.   
     
     
       5. Method of claim 4 further comprising: depositing a silicon passivation dielectric layer on the source and drain metalizations;   depositing a second light shield layer on the silicon passivation dielectric layer; and   etching the second light shield layer to leave a portion of the second light shield layer over each island.   
     
     
       6. Method of claim 5 wherein: the silicon dioxide layer has a thickness between 0.01 and 1.0 micron;   the epitaxial silicon layer has a thickness between 0.01 and 5 microns;   the barrier layer has a thickness between 0.01 and 2 microns; and   the first light shield layer has a thickness between 0.01 and 2 microns.   
     
     
       7. A method for fabricating high mobility thin film transistors as integrated drivers on a substrate, comprising: forming a silicon dioxide layer on a silicon substrate;   removing a portion of the silicon dioxide layer to obtain a plurality of gate dielectric regions of silicon dioxide;   forming a silicon layer on the silicon substrate and the gate dielectric regions;   forming a barrier layer on the silicon layer;   forming a first light shield layer on the barrier layer;   bonding a glass substrate to the first light shield barrier;   removing the silicon substrate;   removing a portion of the silicon layer and of the gate dielectric regions to form a plurability of islands situated on the glass substrate, wherein each island has the silicon layer incorporating at least one gate dielectric region, the barrier layer and the first light shield layer;   forming a glass layer on the islands and exposed portions of the glass substrate on the same surface on which the islands are situated;   removing portions of the glass layer to expose at least the gate dielectric regions of each of the islands;   forming a polysilicon layer on each gate dielectric region of each island;   removing a portion of the polysilicon layer and forming a polysilicon gate situated on each gate dielectric region;   implanting source and drain implantations into the exposed barrier layer on each island, at a thickness greater than the thickness of the gate dielectric region;   annealing the source and drain implantations;   forming a silicon dioxide intermetal dielectric layer on the plurability of the islands and on remaining portions of the layer of glass;   making contact vias through the silicon dioxide intermetal dielectric layer to the source and drain implantations on each island; and   forming and removing portions of source and drain metalizations to the source and drain implantations via the contact vias.   
     
     
       8. Method of claim 7 further comprising: forming a silicon passivation dielectric layer on the source and drain metalizations;   forming a second light shield layer on the silicon passivation dielectric layer; and   removing a first portion of the second light shield layer to leave a second portion of the second light shield layer over each island.   
     
     
       9. Method of claim 8 wherein: the silicon dioxide layer has a thickness between 0.01 and 1.0 micron;   the silicon layer has a thickness between 0.01 and 5 microns;   the barrier layer has a thickness between 0.01 and 2 microns; and   the first light shield layer has a thickness between 0.01 and 2 microns.