Static memory device

Abstract

A static memory device comprises a memory cell array having of a plurality of sections, each including a plurality of memory cells. A selection signal for selecting one section is generated in accordance with a data writing or reading operation. First and second potentials of high level are generated, and one of the potentials are selectively supplied to pairs of bit lines in one of the plurality of sections. In a data writing operation, the pairs of bit lines are precharged to the first potential, e.g., the supply voltage V cc , and in a data reading operation, the pair of bit lines is precharged to the second potential, e.g., V cc -2V f , where V f is a forward voltage of a diode.

What is claimed is: 
     
       1. A static memory device comprising: a memory cell array having a plurality of sections each including a plurality of static memory cells, said static memory cells being arranged at positions where a plurality of pairs of bit lines cross a plurality of word lines;   a selection signal generating circuit for generating a selection signal for selecting one of the sections in accordance with a data writing or reading operation; and   a potential generating circuit for generating first and second potentials of logically high level and supplying the first and second potentials to a pair of bit lines in one of said plurality of sections in response to the selection signal output from said selection signal generating circuit.   
     
     
       2. A static memory device according to claim 1, wherein said potential generating circuit comprises a circuit for supplying the first potential to the pair of bit lines in a data writing operation, and the second potential to the pair of bit lines in a data reading operation, in response to the selection signal. 
     
     
       3. A static memory device according to claim 1, wherein said potential generating circuit comprises a circuit for supplying the first potential to the pair of bit lines for a predetermined period of time in response to the selection signal only in a data reading operation. 
     
     
       4. A static memory device according to claim 1, wherein said potential generating circuit comprises a circuit for supplying the first potential to the pairs of bit lines for a predetermined period of time in response to the selection signal, and thereafter supplying the second potential to the pairs of bit lines in a data reading operation. 
     
     
       5. A static memory device for writing/reading data in/from one memory cell of a plurality of memory cells in response to an address signal, said device comprising: means, having a plurality of word lines, for selecting one of the word lines in response to the address signal;   means, having a plurality of pairs of bit lines, for selecting one of the pairs of bit lines in response to the address signal;   a memory cell array having a plurality of sections each including a plurality of memory cells respectively connected to the word lines and the pairs of bit lines;   means for selecting one of said plurality of sections in response to the address signal; and   means for generating a first potential and a second potential which is lower than the first potential, and supplying one of the first and the second potentials to the pairs of bit lines in the selected section in response to the signal generated from said section selecting means, depending on whether data is written or read.   
     
     
       6. A static memory device according to claim 5, wherein said potential generating means comprises a circuit for supplying the first potential to the pairs of bit lines in a data writing operation, and the second potential to the pairs of bit lines in a data reading operation, in response to a signal output from said section selecting means. 
     
     
       7. A static memory device according to claim 5, wherein said potential generating means comprises a circuit for supplying the first potential to the pairs of bit lines for a predetermined period of time in response to a signal output from said section selecting means, in a data reading operation. 
     
     
       8. A static memory device according to claim 5, wherein said potential generating means comprises a circuit for supplying the first potential to the pairs of bit lines for a predetermined period of time in response to a signal output from said section selecting means, and thereafter supplying the second potential to the pair of bit lines in a data reading operation. 
     
     
       9. A static memory device according to claim 5, wherein said potential generating means comprises: first and second diodes, the anode and the cathode of said second diode being respectively connected to a power source of the memory device and the anode of said first diode, and the cathode of said first diode being connected to the plurality of pairs of bit lines;   an FET transistor, the gate thereof being supplied with a signal output from said section selecting means, one output terminal thereof being connected to the cathode of said first diode, and the other output terminal being grounded; and   a resistor element, one terminal thereof being connected to the cathode of said first diode and the other terminal being grounded.   
     
     
       10. A static memory device according to claim 5, wherein the first potential is a supply voltage V cc  of the memory device and the second potential is V BL  obtained by one of the following equations:   V.sub.BL =V.sub.cc -nV.sub.f and V.sub.BL =V.sub.cc -nV.sub.th     where V f  is a forward voltage of a diode, V th  is a threshold voltage of a MOSFET and n is a whole number.   
     
     
       11. A static memory device comprising: a memory cell array having a plurality of static memory cells, said static memory cells being arranged at positions where a plurality of pairs of bits lines cross a plurality of word lines;   a selection signal generating circuit for generating a selection signal in accordance with a data writing or reading operation; and   a potential generating circuit for generating first and second potentials corresponding to a high logic level and for supplying the first and second potentials to a pair of bit lines in response to the selection signal output from said selection signal generating circuit.   
     
     
       12. A static memory device according to claim 11, wherein said potential generating circuit supplies the first potential to the pair of bit lines in a data writing operation, and the second potential to the pair of bit lines in a data reading operation. 
     
     
       13. A static memory device according to claim 11, wherein said potential generating circuit supplies the first potential to the pair of bit lines for a predetermined period of time in response to the selection signal only in a data reading operation. 
     
     
       14. A static memory device according to claim 11, wherein said potential generating circuit supplies the first potential to the pairs of bit lines for a predetermined period of time in response to the selection signal, and thereafter supplies the second potential to the paris of bit lines in a data reading operation.