Apparatus for receiving and decoding a serial data packet containing the status of a network of single point I/O devices

Abstract

A communication system between a microprocessor based device and a network of a plurality of remote input/output repeater modules uses a synchronous serial communications protocol. The microprocessor based device contains a transmitter module for generating a data packet containing the status of output device connected to remote input/output repeater modules coupled to the network. A receiver module also contained in the microprocessor based device receives and decodes a returned modified data packet that indicates the status of input devices connected to the same or other remote input/output repeater modules also coupled to the network. The receiver module can detect errors in the returned data packet.

We claim: 
     
       1. A receiver module contained in a microprocessor based device for receiving a serial data packet from a plurality of I/O repeater modules connected in series over a synchronous serial communications network, said receiver module comprising: (A) a clock pulse input means for synchronizing said receiver module with said synchronous serial communications network;   (B) a buffer register means, coupled to said synchronous serial communications network, for storing a part of said received serial data packet from said network;   (C) a first shift register means, coupled to said buffer register means, for storing said received serial data packet coupled from said buffer register means and for converting said serial data packet into separate parallel data bits, wherein said data bits include a true data bit and a complement data bit from each of said plurality of I/O repeater modules, said true data bits for indicating the status of each of said I/O modules and wherein said first shift register means further includes separate parallel outputs of said true data bits and of said complement data outputs;   (D) a detector means, coupled to said buffer register means, for decoding an end byte of said received serial data packet to indicate the end of said received serial data packet;   (E) a second buffer register means having an input coupled to the parallel true data bit outputs of said first shift register means, for coupling said parallel true data bits to a parallel data bus in said microprocessor based device;   (F) a comparator means, coupled to said separate parallel outputs of said true data bits and of said complement data outputs of said first shift register, for comparing each of said true data bits with its said complement data bit, for determining if said data bits are valid, and for generating parallel valid data bits if said data bits are valid;   (G) a third buffer register means, coupled to said comparator means, for receiving said parallel valid data bits, said third buffer register means having parallel outputs coupled to said parallel data bus in said microprocessor based device; and   (H) wherein said second buffer register means transfers said true data bits to said microprocessor based device and said third buffer register means transfers said valid data bits to said microprocessor based device.   
     
     
       2. The receiver module of claim 1 wherein said serial data packet received from said synchronous serial communications network consists of an input sync byte, n number of input bytes, where n is the number of said I/O repeater modules connected on said network, and an output sync byte. 
     
     
       3. The receiver module of claim 2 wherein said input bytes received by said receiver module represent status bits for input devices that may be connected to said I/O repeater modules wherein each of said I/O repeater modules inserts its respective said status bits after detecting said input sync byte into said serial data packet. 
     
     
       4. The receiver module of claim 3 wherein said input bytes are split-phase binary encoded having a first bit equal to the true state of said input device and a second bit equal to the complement of the state of said input device. 
     
     
       5. The receiver module of claim 2 wherein said buffer register coupled to said synchronous serial communications network transfers said received serial data packet to said first shift register until said detector detects said output sync byte. 
     
     
       6. The microprocessor based device of claim 1 wherein said microprocessor based device is a programmable logic controller. 
     
     
       7. The microprocessor based device of claim 1 wherein said microprocessor based device is a personal computer. 
     
     
       8. The receiver of claim 1 wherein said synchronous serial communications network is a multiconductor wire cable and said serial data packet is transmitted over said cable. 
     
     
       9. The receiver of claim 1 wherein said synchronous serial communications network is a fiber optic cable and said serial data packet is transmitted over said cable. 
     
     
       10. A receiver module contained in a microprocessor based device for receiving a serial data packet from a plurality of I/O repeater modules connected in series over a synchronous serial communications network, said receiver module comprising: (A) a clock pulse input for synchronizing said receiver with said synchronous serial communications network;   (B) a buffer register coupled to said synchronous serial communications network, said buffer register storing a part of said received serial data packet from said network;   (C) a detector coupled to said buffer register, said detector decoding a start byte and an end byte of said received serial data packet, said start byte to indicate the beginning of said received serial data packet and said end byte to indicate the end of said received serial data packet;   (D) wherein said start byte and said end byte consist of a series of different logic levels including at least one logic high and one logic low;   (E) wherein said detector compares said different logic levels of said start byte and said end byte to determine if all of said different logic levels are logic highs, indicative that said synchronous serial communications network is open circuited; and   (F) wherein said detector compares said different logic levels of said start byte and said end byte to determine if all of said different logic levels are logic lows, indicative that said synchronous serial communications network is short circuited.