Process and device for synchronizing two digital pulse sequences S and RF of the same high frequency

Abstract

Device for synchronizing two constant high frequency digital pulse sequences S and R f comprising a first oscillator producing the frequency sequence R f at the fundamental frequency f and a second oscillator producing the frequency sequence of pulses S also at the frequency f. The second oscillator is a ring oscillator having three loops of inverted logic gates connected in series and corresponding respectively to the frequency f (used if synchronism exists), to a higher frequency f 1 (used if there is a phase lag) and a lower frequency f 2 (used if there is a phase lead) with the choice of the operating loop being made by a multiplexer on the basis of instructions from a phase detector permanently comparing the synchronism, lead or lag state of the sequence S compared with the sequence R f .

We claim: 
     
       1. Synchronization process for maintaining in the vicinity of zero the average phase difference between two digital pulse sequences one of which is a selectable frequency sequence S and the other of which is a reference frequency sequence R f , of the same high average fundamental frequency f consisting of: using a first oscillator to provide the reference frequency sequence R f  of logic signals 0 and 1 at the constant fundamental frequency f;   using a second oscillator for supplying the selectable frequency sequence S of logic signals 0 and 1 on average at the constant theoretical fundamental frequency f and maintaining synchronism with the signals of the reference sequence R f  ;   providing said second oscillator with means enabling it to supply the sequence of pulses S at a selected one of three fixed frequencies, namely;   a) the fundamental frequency f,   b) a second frequency f 1  slightly higher than the fundamental frequency f,   c) a third frequency f 2  slightly lower than the fundamental frequency f;   permanently comparing the phases of the selectable frequency sequence S and the reference sequence R f  using a phase detector in accordance with the following rules:   a) if the leading fronts of the reference sequence R f  pulses lead the leading fronts of the selectable frequency sequence S pulses by up to and including a first time T Rf  then the phase detector notes a synchronism state, and if the leading fronts of the selectable frequency sequence S pulses lag the leading fronts of the references sequence R f  pulses by more than the first time T Rf  then the phase detector notes a lag state;   b) if the leading fronts of the selectable frequency sequence S pulses lead the leading fronts of the reference sequence R f  pulses by up to and including a second time T s  then the phase detector notes the synchronism state, and if the leading fronts of the reference sequence R f  pulses lag the leading fronts of the selectable frequency sequence S pulses by more than the second time T s  then the phase detector notes a lead state;   controlling the second oscillator on the basis of information from the phase detector in such a way that it oscillates at:   the fundamental frequency f if the phase detector has noted a synchronism state,   the second frequency f 1  if the phase detector has noted the lag state, and   the third frequency f 2  if the phase detector has noted the lead state.   
     
     
       2. Synchronization process according to claim 1, usable for large, accidental phase shifts, particularly during the starting up of the process further consisting of using particular determination rules for the lead or lag states of the selectable frequency sequence S compared with the reference sequence R f  in accordance with whether: the phase detector notes a lag state of the selectable frequency sequence S pulses compared with the reference sequence R f  pulses, which will occur when the leading front of the reference sequence R f  pulses occurs during the state 0 of the selectable frequency sequence S pulses; or   the phase detector notes a lead state of the selectable frequency sequence S compared with the reference sequence R f  pulses, which will occur when the leading front of the reference sequence R f  pulses occurs during the state 1 of the selectable frequency sequence S pulses.   
     
     
       3. Synchronization device for maintaining in the vicinity of zero the average phase difference between two digital pulse sequences one of which is a selectable frequency sequence S and the other of which is a reference frequency sequence R f , of the same high fundamental frequency f comprising: a reference oscillator for producing the pulse sequence for the reference frequency R f  of logic signals 0 and 1 at the constant fundamental frequency f;   a ring oscillator comprising three loops, each of which has an uneven number of inverted logic gates, including a first loop wherein the oscillating frequency corresponds to the nominal frequency f of the reference frequency R f  pulses, a second loop having an oscillating frequency f 1  slightly higher than the nominal frequency f and a third loop having an oscillating frequency f 2  slightly lower than the nominal frequency f;   a phase detector receiving the reference frequency R f  pulses and the selectable frequency S pulses to determine the synchronism, lead or lag state of the selected frequency S sequence compared with the reference frequency R f  sequence; and for providing an output signal indicative of the state of the selected frequency sequence;   a multiplexer responsive to the output signal of said phase detector for selecting between one of said preceding loops in said ring oscillator;   coupling means located between the multiplexer and the phase detector for enabling the latter to direct the selection of the multiplexer in favour of the:   first loop if it has detected a state situation of the pulses S compared with the pulses R f , wherein the nominal frequency f corresponds to the oscillating frequency,   second loop if it has detected a lag state, and   third loop if it has detected a lead state.   
     
     
       4. Synchronization device according to claim 3, characterized in that the rules for the determination of the synchronism, lead or lag state are as follows: if the leading fronts of the reference sequence R f  pulses lead the leading fronts of the selectable frequency sequence S pulses by up to and including a first time T Rf  then the phase detector notes a synchronism state, and if the leading fronts of the selectable frequency sequence S pulses lag the leading fronts of the references sequence R f  pulses by more than the first time T Rf  then the phase detector notes a lag state;   b) if the leading fronts of the selectable frequency sequence S pulses lead the leading fronts of the reference sequence R f  pulses by up to and including a second time T s  then the phase detector notes the synchronism state, and if the leading fronts of the reference sequence R f  pulses lag the leading fronts of the selectable frequency sequence S pulses by more than the second time T s  then the phase detector notes a lead state.   
     
     
       5. Synchronization device according to claim 3, characterized in that the determination rules for the synchronism, lead or lag states are as follows: the phase detector notes a lag state of the selectable frequency sequence S pulse compared with the reference sequence R f  pulses, when the leading front of the pulses R f  occurs during the state zero of the selectable frequency sequence S pulse;   the phase detector notes a lead state of the selectable frequency sequence S pulses compared with the reference sequence pulses, when the leading front of the reference sequence R f  pulses occurs during the state 1 of the selectable frequency S pulses.   
     
     
       6. Synchronization process for maintaining in the vicinity of zero the average phase difference between two digital pulse sequences one of which is a selectable frequency sequence S and the other of which is a reference frequency sequence R f , of the same high fundamental frequency f consisting of: using a first sequence oscillator to provide the reference frequency R f  of logic signals 0 and 1 at the constant fundamental frequency f;   using a second oscillator for supplying the selectable frequency sequence S of logic signals 0 and 1 at the constant theoretical fundamental frequency f and maintaining synchronism with the signals of the reference sequence R f  ;   providing said second oscillator with means enabling it to supply the sequence of pulses S at a selected one of three fixed frequencies, namely:   a) the fundamental frequency f,   b) a second frequency f 1  slightly higher than the fundamental frequency f,   c) a third frequency f 2  slightly lower than the fundamental frequency f;   permanently comparing the phases of the selectable frequency sequence S and the reference sequence R f  using a phase detector in accordance with the following rules:   a) if the leading fronts of the reference sequence R f  pulses lead the leading fronts of the selectable frequency sequence S pulses by up to and including a first time T Rf  then the phase detector notes a synchronism state, and if the leading fronts of the selectable frequency sequence S pulses lag the leading fronts of the references sequence R f  pulses by more than the first time T Rf  then the phase detector notes a lag state;   b) if the leading fronts of the selectable frequency sequence S pulses lead the leading fronts of the reference sequence R f  pulses by up to and including a second time T s  then the phase detector notes the synchronism state, and if the leading fronts of the reference sequence R f  pulses lag the leading fronts of the selectable frequency sequence S pulses by more than the second time T s  then the phase detector notes a lead state,   c) in the absence of synchronism, the following rules are used for determining the lead or lag state:   the phase detector notes a lag state when the leading front of the reference sequence pulses occurs during the state 0 of the selectable frequency sequence S pulses;   the phase detector notes a lead state when the leading front of the reference sequence R f  pulses occurs during the state 1 of the selectable frequency sequence pulses;   controlling the second oscillator on the basis of information from the phase detector in such a way that it oscillates:   at said fundamental frequency f if the phase detector has noted a synchronism state;   at said frequency f 1  if the phase detector has noted a lag state; and   at said frequency f 2  if the phase detector has noted a lead state.