Power saving impedance transformation circuit for CCD image sensors

Abstract

A power saving impedance transformation circuit for receiving a d-c biased signal comprises a junction transistor connected to operate as an emitter follower, means for connecting the base of the transistor to receive the signal, an operational amplifier having both inverting and non-inverting inputs, a first resistor connected between the emitter of the transistor and the operational amplifier inverting input, a second resistor equal to the first resistor in resistance and having one end connected to the operational amplifier inverting input, resistive means for connecting the other end of the second resistor to a first voltage source of a polarity which, in cooperation with the signal, forward biases the emitter-base junction of the transistor, the emitter-base junction of the transistor receiving its forward bias from the first voltage source exclusively through the first and second resistors and the resistive means, and means for connecting the collector of the transistor to a second voltage source of a polarity opposite to that of the first voltage source.

What is claimed is: 
     
       1. A power saving impedance transformation circuit for receiving a d-c biased signal comprising: a transistor having an emitter, a collector, and a base, an emitter-base junction between said emitter and said base, and a collector-base junction between said collector and said base;   means for connecting the base of said transistor to receive said signal;   an operational amplifier having both inverting and non-inverting inputs and an output, said operational amplifier output comprising the output of said impedance transformation circuit;   a first resistor connected between the emitter of said transistor and said operational amplifier inverting input;   a second resistor substantially equal to said first resistor in resistance and having one end connected to said operational amplifier inverting input;   a third resistor connecting the non-inverting input to ground;   variable resistive means for connecting the other end of said second resistor to a first voltage source of a desired polarity to provide a variable voltage, the variable voltage being selected in cooperation with said signal, to forward biases the emitter-base junction of said transistor to achieve low power dissipation;   the emitter-base junction of said transistor receiving its forward bias from said first voltage source exclusively through said first and second resistors and said resistive means; and   means for connecting the collector of said transistor to a second voltage source of a polarity opposite to that of said first voltage source.   
     
     
       2. The power saving impedance transformation circuit of claim 1 in which said transistor is an n-p-n transistor, said first voltage source is a negative voltage source and said second voltage source is a positive voltage source. 
     
     
       3. The power saving impedance transformation circuit of claim I further comprising: a third resistor having one end connected to said operational amplifier non-inverting input; and   means for connecting the other end of said third resistor to a point of reference potential intermediate said first and second voltage sources.   
     
     
       4. The power saving impedance transformation circuit of claim 3 further comprising a feedback resistor connected between said operational amplifier output and said operational amplifier inverting input. 
     
     
       5. The power saving impedance transformation circuit of claim 4 further comprising: a capacitor having one side connected to said other end of said second resistor; and   means for connecting the other side of said capacitor to said point of reference potential.   
     
     
       6. The power saving impedance transformation circuit of claim 5 in which said transistor is an n-p-n transistor, said first voltage source is a negative voltage source, said second voltage source is a positive voltage source, and said intermediate potential is ground. 
     
     
       7. In combination with a CCD image sensor having at least one output and a correlated double sample and hold circuit connected to receive said output, said sample and hold circuit producing a d-c biased signal, a power saving impedance transformation circuit for receiving said signal comprising: a transistor having an emitter, a collector, and a base, an emitter-base junction between said emitter and said base, and a collector-base junction between said collector and said base;   means for connecting the base of said transistor to receive said signal:   an operational amplifier having both inverting and non-inverting inputs and an output, said operational amplifier output providing the output of said impedance transformation circuit;   a first resistor connected between the emitter of said transistor and said operational amplifier inverting input;   a second resistor substantially equal to said first resistor in resistance and having one end connected to said operational amplifier inverting input;   resistive means for connecting the other end of said second resistor to a first voltage source of a polarity which, in cooperation with said signal, forward biases the emitter-base junction of said transistor;   the emitter-base junction of said transistor receiving its forward bias from said first voltage source exclusively through said first and second resistors and said resistive means; and   means for connecting the collector of said transistor to a second voltage source of a polarity opposite to that of said first voltage source.   
     
     
       8. The combination of claim 7 in which said transistor is an n-p-n transistor, said first voltage source is a negative voltage source and said second voltage source is a positive voltage source. 
     
     
       9. The combination of claim 7 in which said power saving impedance transformation circuit further comprises: a third resistor having one end connected to said operational amplifier non inverting input; and   means for connecting the other end of said third resistor to a point of reference potential intermediate said first and second voltage sources.   
     
     
       10. The combination of claim 9 in which said power saving impedance transformation circuit further comprises a feedback resistor connected between said operational amplifier output and said operational amplifier inverting input. 
     
     
       11. The combination of claim 10 in which said power saving impedance transformation circuit further comprises: a capacitor having one side connected to said other end of said second resistor; and   means for connecting the other side of said capacitor to said point of reference potential.   
     
     
       12. The combination of claim 11 in which said transistor is an n-p-n transistor, said first voltage source is a negative voltage source, said second voltage source is a positive voltage source, and said intermediate potential is ground. 
     
     
       13. In combination with a CCD image sensor having a plurality of outputs and a plurality of correlated double sample and hold circuits each connected to receive a respective one of aid outputs, each of sample and hold circuits producing a respective d-c biased single, a plurality of low power dissipation circuits for receiving respective ones of said signals, a plurality of power saving impedance transformation circuits for receiving respective ones of said signals each comprising: a transistor having an emitter, a collector, and a base, an emitter-base junction between said emitter and said base, and a collector-base junction between said collector and said base;   means for connecting the base of said transistor to receive a respective one of said signals;   an operational amplifier having both inverting and non-inverting inputs and an output, said operational amplifier output comprising the output of said impedance transformation circuit;   a first resistor connected between the emitter of said transistor and said operational amplifier inverting input;   a second resistor substantially equal to said first resistor in resistance and having gone end connected to said operational amplifier inverting input;   a third resistor connecting the non-inverting input to ground;   variable resistive means for connecting the other end of said second resistor to a first voltage source of a desired polarity to provide a variable voltage, the variable voltage being selected in cooperation with a respective one of said signals, to forward biases the emitter-base junction of said transistor to achieve low power dissipation;   the emitter-base junction of said transistor receiving its forward bias from said first voltage source exclusively through said first and second resistors and sad resistive means; and   means for connecting the collector of said transistor to a second voltage source of a polarity opposite to that of said first voltage source.   
     
     
       14. The combination of claim 13 in which said transistor is an n-p-n transistor, said first voltage source is a negative voltage source and said second voltage source is a positive voltage source. 
     
     
       15. The combination of claim 13 in which each of said power saving impedance transformation circuits further comprises: a third resistor having one end connected to said operational amplifier non-inverting input; and   means for connecting the other end of said third resistor to a point of reference potential intermediate said first and second voltage sources.   
     
     
       16. The combination of claim 15 in which said power saving impedance transformation circuit further comprises a feedback resistor connected between said operational amplifier output and said operational amplifier inverting input. 
     
     
       17. The combination of claim 16 in which each of said power saving impedance transformation circuits further comprises: a capacitor having one side connected to said other end of said second resistor; and   means for connecting the other side of said capacitor to said point of reference potential.   
     
     
       18. The combination of claim 17 in which said transistor is an n-p-n transistor, said first voltage source is a negative voltage source, said second voltage source is a positive voltage source, and said intermediate potential is ground.