Semiconductor memory device with write-per-bit function

Abstract

A semiconductor memory device equipped with a write-per-bit function includes a data-in circuit, a write-per-bit decision circuit, and a write buffer circuit. The data-in circuit and the write-per-bit decision circuit are connected to the write buffer circuit through a single common signal bus line, whereby an output signal from the data-in circuit and an output signal from the write-per-bit decision circuit are supplied to the write buffer circuit through the single signal line. The chip size as well as the number of signal lines can be reduced through such common use of the single signal line.

What is claimed is: 
     
       1. A semiconductor memory device having a plurality of data input/output terminals and a write-per-bit function, said memory device comprising: a memory cell array in a matrix array form;   a data-in circuit having an input terminal and an output terminal, said input terminal connected to one of said data input/output terminals, for taking-in an input data therein and outputting a write data to said output terminal;   a write-per-bit decision circuit having an external signal input terminal and an output terminal, for outputting a control signal which permits or prohibits writing of said write data from said data-in circuit in said memory cell array in response to an external signal applied to said external signal input terminal;   a write buffer circuit having an input terminal for taking-in said write data from said data-in circuit and an output terminal for outputting said write data to said memory cell array, said write buffer circuit being activated or inactivated in response to the control signal from said write-per-bit decision circuit; and   a single common signal bus line commonly connecting said output terminal of said data-in circuit and said output terminal of said write-per-bit decision circuit to said input terminal of said write buffer circuit.   
     
     
       2. A semiconductor memory device according to claim 1, in which said data-in circuit and said write-per-bit decision circuit output respectively output signals which are supplied to said write buffer circuit through said common signal bus line. 
     
     
       3. A semiconductor memory device having a plurality of data input/output terminals and write enable signal terminals and a write-per-bit function, said memory device comprising: a data-in circuit having input terminals and an output terminal, said input terminals respectively connected to one of said data input/output terminals and one of said write enable signal terminals, for taking-in an input data therein and outputting a write data to said output terminal;   a write-per-bit decision circuit having input terminals respectively connected to the one of said data input/output terminals, the one of said write enable signal terminals and a row address strobe signal terminal, for outputting a control signal which permits or prohibits writing of said write data from said data-in circuit in said memory cell array in response to a row address strobe signal applied to said row address strobe signal terminal;   a write buffer circuit having an input terminal for taking-in said write data from said data-in circuit and an output terminal for outputting said write data to said memory cell array, said write buffer circuit being activated or inactivated in response to the control signal from said write-per-bit decision circuit; and   a single common signal bus line commonly connecting said output terminal of said data-in circuit and said output terminal of said write-per-bit decision circuit to said input terminal of said write buffer circuit.   
     
     
       4. A semiconductor memory device according to claim 3, in which said data-in circuit and said write-per-bit decision circuit output respectively output signals which are supplied to said write buffer circuit through said common signal bus line.