Semiconductor memory cell and manufacturing method thereof

Abstract

A semiconductor memory cell and device having a tubular formed storage electrode of a capacitor through which a bit line passes. The source, gate and drain of a switching transistor are arranged in a direction parallel to a longitudinal axis of the tubular storage electrode. An active region also is arranged in a parallel or superposing direction relative to the bit line and in a perpendicular direction relative to the word line. A manufacturing method thereof includes forming a switching transistor, forming a part of the capacitor storage electrode connected with the drain of the switching transistor, forming an oxide film side wall, forming a bit line in parallel to a longitudinal axis of the active region, forming a capacitor storage electrode of tubular form, covering the surface of the capacitor storage electrode with a capacitor dielectric film, and forming a plate electrode of the capacitor thereon.

What is claimed is: 
     
       1. A semiconductor memory device, comprising: a plurality of switching transistors each having a gate and source and drain regions formed in an active region of a semiconductor substrate;   word lines coupled to the gates of the switching transistors through an insulating layer;   bit lines coupled to the source regions of the switching transistors;   tubular storage electrodes coupled to the drain regions of the switching transistors, each tubular storage electrode having an interior region, wherein a bit line passes through the interior regions of the tubular storage electrodes;   a dielectric layer on the tubular storage electrodes; and   a plate electrode on the dielectric layer.   
     
     
       2. The semiconductor memory device as claimed in claim 1, wherein the gate and source and drain regions of each switching transistor are linearly arranged in a first direction, wherein a bit line linearly passes through the interior region of one or more tubular storage electrodes in a second direction, wherein the first direction is substantially parallel to the second direction. 
     
     
       3. The semiconductor memory device as claimed in claim 2, wherein tubular storage electrodes are positioned substantially above at least a portion of the switching transistors. 
     
     
       4. The semiconductor memory device as claimed in claim 2, wherein the word lines are positioned substantially perpendicular to the first and second directions. 
     
     
       5. The semiconductor memory device as claimed in claim 1, wherein at least a portion of each active region is linearly arranged in a first direction, wherein a bit line linearly passes through the interior region of one or more tubular storage electrodes in a second direction, wherein the first direction is substantially parallel to the second direction. 
     
     
       6. The semiconductor memory device as claimed in claim 5, wherein tubular storage electrodes are positioned substantially above at least a portion of the linearly arranged portions of the active regions. 
     
     
       7. The semiconductor memory device as claimed in claim 5, wherein the word lines are positioned substantially perpendicular to the first and second directions. 
     
     
       8. In a semiconductor memory device having a switching transistor formed in an active region, a word line and a bit line, an improved storage capacitor comprising: a tubular storage electrode having an interior region, wherein the bit line passes through the interior region of the tubular storage electrode;   a dielectric layer on the tubular storage electrode; and   a plate electrode on the dielectric layer.   
     
     
       9. The improved storage capacitor as claimed in claim 8, wherein at least a portion of the tubular storage electrode is positioned substantially above at least a portion of the switching transistor. 
     
     
       10. The improved storage capacitor as claimed in claim 8, wherein the bit line passing through the interior region of the tubular storage electrode is positioned substantially perpendicular to the word line. 
     
     
       11. An improved cell for a semiconductor memory, comprising: an active region including first and second diffusions of a switching transistor formed in a semiconductor substrate;   an insulating layer formed on the semiconductor substrate and having first and second contact holes;   a word line electrically isolated from the semiconductor substrate including a portion thereof formed as a gate electrode of the switching transistor;   a tubular storage electrode having an interior region, the tubular storage electrode being electrically coupled through the first contact hole to the first diffusion;   a bit line electrically coupled to the second diffusion through the second contact hole, wherein the bit line passes through the interior region of the tubular storage electrode;   a dielectric layer on the tubular storage electrode; and   a plate electrode on the dielectric layer.   
     
     
       12. The cell as claimed in claim 11, wherein the first and second diffusions of the switching transistor are linearly arranged in a first direction, wherein the bit line linearly passes through the interior region of the tubular storage electrode in a second direction, wherein the first direction is substantially parallel to the second direction. 
     
     
       13. The cell as claimed in claim 11, wherein the tubular storage electrode is positioned substantially above at least a portion of the switching transistor. 
     
     
       14. The cell as claimed in claim 11, wherein the word line is positioned substantially perpendicular to the first and second directions. 
     
     
       15. A method for manufacturing a semiconductor memory cell comprising: (1) forming a switching transistor with a gate, source and drain in an active region in a semiconductor substrate, with the active region defined by a field oxide film that electrically isolates each active region;   (2) forming a first element of a capacitor storage electrode connected to the drain of the switching transistor by depositing a first oxide film, opening a buried contact in the first oxide film, depositing a first polysilicon film on the overall surface, depositing a second oxide film, and patterning the second oxide film and the first polysilicon film perpendicular to the longitudinal axis of the active region;   (3) forming an oxide film side wall beside the first polysilicon film by depositing an oxide film on the overall surface and etching back the oxide film;   (4) forming a bit line by opening a bit line contact, depositing a second polysilicon film, etching back the second polysilicon film, depositing a refractory metal film on the second polysilicon film, depositing a third oxide film, and patterning the third oxide film, the refractory metal film, and the second polysilicon film parallel to the longitudinal axis of the active region;   (5) depositing a fourth oxide film, and patterning the fourth oxide film and the second oxide film parallel to the longitudinal axis of the active region to expose portions of the first polysilicon film;   (6) forming a capacitor storage electrode in tubular form by depositing a third polysilicon film, and patterning the third polysilicon film and the first polysilicon film, wherein the capacitor storage electrode is formed by the remaining portions of the first and third polysilicon films; and   (7) covering the surface of the capacitor storage electrode with a capacitor dielectric film, and forming a plate electrode of the capacitor thereon.   
     
     
       16. A method for manufacturing a semiconductor memory cell comprising: (1) forming a switching transistor with a gate, source and drain in an active region in a semiconductor substrate, with the active region defined by a field oxide film that electrically isolates the active region;   (2) forming a first element of a capacitor storage electrode connected to the drain of the switching transistor by depositing a first oxide film, opening a buried contact in the first oxide film, depositing a first polysilicon film on the overall surface, depositing a second oxide film, and patterning the second oxide film and the first polysilicon film perpendicular to the longitudinal axis of the active region;   (3) forming an oxide film side wall beside the first polysilicon film by depositing an oxide film on the overall surface and etching back the oxide film;   (4) forming a bit line by opening a bit line contact, depositing a second polysilicon film, etching back the second polysilicon film, depositing a refractory metal film on the second polysilicon film, depositing a third oxide film, and patterning the third oxide film, the refractory metal film, and the second polysilicon film parallel to the longitudinal axis of the active region;   (5) depositing a first isolation film of a material with greater etching selectivity than the second oxide film, the first polysilicon film and a third polysilicon film, patterning the first isolation film to cover the bit line in a parallel manner, depositing the third polysilicon film and a second isolation film of a material with greater etching selectivity than the second oxide film and the first and third polysilicon films, and patterning the second isolation film so as to cover the bit line in a parallel manner;   (6) etching the third polysilicon film, the second oxide film, and the first polysilicon film in turn by using the second isolation film as a mask layer and thereby forming an upper element of the capacitor storage electrode;   (7) forming a storage electrode of the capacitor by depositing a fourth polysilicon film, dry etching the fourth polysilicon film and then removing the second isolation film, thereby forming a side wall projection connecting the third polysilicon film above the bit line and the first polysilicon film under the bit line; and   (8) forming a dielectric film of the capacitor and a plate electrode of the capacitor on the surface of the storage electrode of the capacitor.   
     
     
       17. A method for manufacturing a semiconductor memory cell as claimed in claim 5, characterized in that the first and second isolation films in the fifth step comprise nitride.