US5331289AExpiredUtilityPatentIndex 73
Translinear fT multiplier
Est. expiryFeb 8, 2013(expired)· nominal 20-yr term from priority
Inventors:PRICE BURT L
G06G 7/163
73
PatentIndex Score
14
Cited by
7
References
3
Claims
Abstract
A translinear f T multiplier has a pair of differential transistor amplifiers, each pair having commonly coupled emitters, with the base of one transistor of one pair being coupled to the base of one transistor of the other pair and the collectors of the pair being cross-coupled. A diode network provides three parallel diode paths from a reference voltage, two paths being coupled to receive an input signal and to the bases of the other transistors of each pair and the third path being coupled to a constant current source and to the bases of the first transistors of each pair. The resulting circuit configuration accommodates varying transition times.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1. A bipolar translinear f T multiplier of the type having a pair of differential transistor amplifiers with the emitters of each pair coupled together to a constant current source, with the base of one transistor of the first pair being coupled to the base of one transistor of the second pair, and with the collectors cross-coupled to provide a differential output current comprising: a diode network having three parallel paths coupled between a reference potential and for two of the paths a differential input signal and for the third path a constant current source, the constant current source being coupled to the one base of each transistor pair and the differential input signal being coupled across the other bases of the first and second pairs.
2. The multiplier according to claim 1 further comprising a differential predriver circuit to which the differential input signal is applied, the output of the differential predriver circuit being applied across the other bases of the pair of differential transistors and being coupled to the two paths of the diode network.
3. The multiplier according to claim 1 further comprising a common-base transistor in series with each collector of the pair of differential transistors for improving the speed of the multiplier by reducing the voltage swing on the collectors.Cited by (0)
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