Integrated circuit and layout system therefor

Abstract

In the chip layout of an LSI, a layout near bonding pads is efficiently optimized. Especially in a chip having a large number of pins, an increase in chip size caused by pad necks can be prevented. Normal functional macro-blocks are arranged in an inner region of the LSI. On the other hand, input/output blocks including corner blocks are arranged at the peripheral portion of the LSI. In addition, pads separated from the input/output blocks are arranged on the LSI including portions near the corner blocks, and the input/output blocks and the pads are connected to each other through wiring lines.

What is claimed is; 
     
       1. An integrated circuit comprising: a plurality of macro-blocks arranged in an inner region of a semiconductor chip;   a plurality of input/output blocks arranged at a peripheral portion of said macro-blocks;   bonding pads respectively arranged between said input/output blocks and an outer frame of said semiconductor chip;   a first layout obtained by performing predetermined wiring between said macro-blocks and between said macro-blocks and said input/output blocks;   a second layout obtained by performing wiring between said input/output blocks and said corresponding bonding pads,   wherein said bonding pads are arranged near corners of said semiconductor chip, and said second layout has a bent wiring pattern between input/output blocks corresponding to said bonding pads arranged near the corners of said semiconductor chip,   wherein said input/output blocks and said bonding pads corresponding to said input/output blocks respectively include terminals each having a wiring drawing position set on a basis of relationships between said input/output blocks and said bonding pads, and wherein said bonding pads are connected to said input/output blocks such that said terminals are connected to each other through wiring lines,   a shape and a drawing direction of a wiring of said second layout being determined by a positional relationship between said input/output blocks and said bonding pads corresponding to said input/output blocks, said input/output blocks being arranged at positions near said bonding pads corresponding to said input/output blocks.   
     
     
       2. An integrated circuit according to claim 1, wherein said bonding pads are arranged on an outer frame of said semiconductor chip. 
     
     
       3. An integrated circuit according to claim 1, wherein said bonding pads arranged near the corners of said semiconductor chip are connected to said input/output blocks corresponding to said bonding pads through the wiring pattern of said second layout drawn in parallel to one side of said semiconductor chip on which said corresponding input/output blocks are arranged. 
     
     
       4. A layout system for an integrated circuit, comprising: input/output block arranging means for initially arranging a plurality of input/output blocks at a peripheral portion of a semiconductor chip, separating bonding pads from said input/output blocks, and arranging the separated bonding pads between said input/output blocks and an outer frame of said semiconductor chip;   functional macro-block arranging means for arranging a plurality of functional macro-blocks in an inner region of said semiconductor chip;   interwiring means for performing wiring between said bonding pads and said corresponding input/output blocks; and   interwiring means for performing predetermined wiring between said functional macro-blocks and between said functional macro-blocks and said input/output blocks, wherein said interwiring means includes wiring pattern determining means for determining a wiring shape.   
     
     
       5. A system according to claim 4, wherein said wiring pattern determining means includes means for determining a wiring shape and a drawing direction on a basis of positional relationships between said input/output blocks and said bonding pads. 
     
     
       6. A layout system for an integrated circuit, comprising: input/output block arranging means for initially arranging a plurality of input/output blocks at a peripheral portion of a semiconductor chip, separating bonding pads from said input/output blocks, and arranging the separated bonding pads between said input/output blocks and an outer frame of said semiconductor chip;   functional macro-block arranging means for arranging a plurality of functional macro-blocks in an inner region of said semiconductor chip;   interwiring means for performing wiring between said bonding pads and said corresponding input/output blocks; and   interwiring means for performing predetermined wiring between said functional macro-blocks and between said functional macro-blocks and said input/output blocks,   wherein said interwiring means for performing wiring between said input/output blocks and said bonding pads includes wiring pattern determining means for determining a wiring shape and a drawing direction on a basis of positional relationships between said input/output blocks and said bonding pads, terminal setting means for setting terminals on wiring line drawing sides determined by said wiring pattern setting means, and wiring means for forming wiring lines for connecting said terminals set by said terminal setting means.   
     
     
       7. A system according to claim 6, wherein said input/output block arranging means initially arranges said input/output blocks and said bonding pads on a basis of an underlying frame file in which pad coordinates are described within a frame having a predetermined size, a pad assignment file for designating an input/output block to be assigned to a specific pad, an input/output block library file, and circuit connecting information. 
     
     
       8. A system according to claim 6, further comprising input/output block arrangement improving means for improving an arrangement of said initially arranged input/output blocks in accordance with connection relationships between said input/output blocks and said functional marco-blocks. 
     
     
       9. A system according to claim 1, wherein, when a wiring region is short, only said input/output blocks are moved, and said bonding pads are fixed to initially arranged positions. 
     
     
       10. A system according to claim 6, further comprising bonding pad arrangement improving means for moving bonding pads within a predetermined movable range such that a bent wiring pattern is changed into a linear wiring pattern when the bent wiring pattern is determined by said wiring pattern setting means. 
     
     
       11. A system according to claim 10, wherein said bonding pads have a rectangular shape with a drawn side from which the wiring pattern of said second layout is drawn, said terminals of said bonding pads are set at positions further than end portions of the drawn sides thereof by a half of a wiring width, and said terminals of said input/output blocks are set at positions further than end portions of a side of said semiconductor chip, on which said input/output blocks are arranged, by half of a sum of the wiring width and a minimum interwiring interval.