Soft error immune CMOS static RAM cell

Abstract

Soft error immunity of a storage cell is greatly increased by division of a storage node into at least two portions and location of those portions on opposite sides of an isolation structure, such as a well of a conductivity type opposite to that of the substrate in which transistors of the memory cell may also be formed. The isolation structure thus limits collection of charge to only one of the portions of the storage node and reduces charge collection efficiency to a level where a critical amount of charge cannot be collected in all but a statistically negligible number of cases when such charge is engendered by impingement by ionizing radiation, such as energetic alpha particles. The layout of the memory cell having this feature also advantageously provides a simplified topology for the formation of additional ports comprising word line access transistors and bit lines.

Having thus described my invention, what I claim as new and desire to secure by Letters Patent is as follows: 
     
       1. A memory cell comprising in combination: a storage node including at least two spatially separated depletion regions formed in a semiconductor substrate of a first conductivity type;   a well of a second conductivity type formed in said semiconductor substrate and located between said at least two spatially separated depletion regions for reducing collection of charge engendered by ionizing radiation in the vicinity of a first of said at least two spatially separated depletion regions at a second of said at least two spatially separated depletions regions.   
     
     
       2. A memory cell comprising in combination: a semiconductor substrate of a first conductivity type;   a well of a second conductivity type formed in said substrate;   two cross-coupled invertors;   each of said cross-coupled invertors including at least three transistors, two of said at least three transistors formed in said semiconductor substrate of said first conductivity type and one of said at least three transistors formed in said well of said second conductivity type;   each of said cross-coupled invertors including a storage node comprised of two spatially separated depletion regions formed by said two of said at least three transistors and;   said well of a second conductivity type located between said two spatially separated depletion regions for reducing collection of charge engendered by ionizing radiation in the vicinity of a first of said two spatially separated depletion regions as a second of said two spatially separated depletion regions.   
     
     
       3. A memory cell as recited in claim 2, wherein said transistors are field effect transistors. 
     
     
       4. A memory cell as recited in claim 2, wherein said transistors are complementary field effect transistors. 
     
     
       5. A memory cell as recited in claim 2, further including a bit line and a word line access transistor connected between said storage node and said bit line. 
     
     
       6. A memory cell as recited in claim 2, further including at least two bit lines and at least two word line access transistors, each said word line access transistor being connected between said storage node and a respective one of said at least two bit lines. 
     
     
       7. A memory cell as recited in claim 2, further including a bit line and a word line access transistor connected between said storage node and said bit line. 
     
     
       8. A memory cell as recited in claim 2, further including at least two bit lines and at least two word line access transistors, each said word line access transistor being connected between said storage node and a respective one of said at least two bit lines. 
     
     
       9. A memory cell as recited in claim 2, wherein said semiconductor substrate is a P-type semiconductor substrate. 
     
     
       10. A memory cell as recited in claim 2, wherein said two cross-coupled amplifiers include complementary metal oxide semiconductor field effect transistors.