Digital processing apparatus for simultaneously processing two or more jobs by switching between two or more instruction address register

Abstract

A digital signal processing apparatus according to the present invention includes two or more address registers associated with at least one of an instruction memory, a data memory, or a coefficient memory and two or more data registers associated with a computing block, and these two or more registers are duty cycled switched between different jobs being simultaneously processed by the computing block to enable efficient processing on a single chip of jobs that can be processed with different processing speeds, such as jobs suited for high speed processing or low speed processing.

What is claimed is: 
     
       1. A digital signal processing apparatus for simultaneously processing two or more jobs and comprising at least an instruction memory, a data memory and a computing block, which operates according to instruction clocks cyclicly supplied from a source, operatively connected to each other and wherein the improvement resides in that: (a) two or more instruction address registers are associated with the instruction memory for separately supplying instruction address data for different jobs; and   (b) switching means supplied with the instruction clocks for cyclicly switching between the two or more instruction address registers according to a predetermined pattern of the instruction clocks to cyclicly connect the instruction address registers to the instruction memory for cyclicly supplying instruction address data from a current job and then one or more previous jobs to the instruction memory to enable processing by the computing block to by cyclicly switched between the current job and one or more previous jobs, wherein the jobs to be processed require different processing times and further wherein the predetermined pattern of instruction clocks is selected so that the switching means connects the instruction memory to a first one of the instruction address registers for a first continuous period of N instruction clocks for a job requiring a longest processing time and to another of the instruction address registers for a second continuous period of M instruction clocks for a job requiring a second longest processing time, where N and M are both integers and N>M.   
     
     
       2. The digital signal processing apparatus according to claim 1 further comprising two or more data address registers which are associated with the data memory for separately supplying data address data for different jobs and wherein the data address registers have inputs and outputs and the switching means cyclicly connects the outputs of the two or more data address registers, one at a time, to the data memory in accordance with the predetermined pattern of instruction clocks to cyclicly supply data address data for a current job and then one or more previous jobs to the data memory to enable processing by the computing block to be cyclicly switched between the current job and the one or more previous jobs. 
     
     
       3. The digital signal processing apparatus according to claim 1 wherein the computing block has inputs and an output and two or more computed data registers which are associated with the computing block for storing and then supplying computed data and wherein the computed data registers have inputs connected to the output of the computing block and outputs which are cyclicly connected by the switching means, one at a time, to one of the inputs of the computing block to cyclicly supply computed data for a current job and then one or more previous jobs to the computing block in accordance with the predetermined pattern of instruction clocks to enable processing by the computing block to be cyclicly switched between the current job and the one or more previous jobs. 
     
     
       4. The digital signal processing apparatus according to claim 1, further comprising a coefficient memory and two or more coefficient address registers which are associated with the coefficient memory for supplying coefficient address information for different jobs and wherein the two or more coefficient address registers are cyclicly connected with the coefficient memory by the switching means, one at time, in accordance with the predetermined pattern of instruction clocks to cyclicly supply coefficient address data for a current job and then one or more previous jobs to the coefficient memory to enable processing by the computing block to be cyclicly switched between the current job and the one or more previous jobs. 
     
     
       5. A digital signal processing apparatus for simultaneously processing two jobs and comprising at least a computing block which operates according to instruction clocks cyclicly supplied from a source, a data memory connected to the computing block for supplying data to the computing block, an instruction memory connected to the data memory and the computing block for supplying address instructions to the data memory and the computing block for processing the two jobs and wherein the improvement comprises: (a) two instruction address registers for respectively storing job processing instruction addresses for a current job and a previous job; and   (b) switching means supplied with the instruction clocks for cyclicly connecting one of the instruction address registers at a time to the instruction memory according to a predetermined, cyclical pattern of the instruction clocks for cyclicly supplying the job processing instruction addresses to the instruction memory for a current job and then a previous job to enable job processing to be cyclicly switched between a current job and, wherein the jobs to be processed require different processing times and further wherein the predetermined pattern of instruction clocks is selected so that the switching means connects the instruction memory to a first one of the instruction address registers for a first continuous period of N instruction clocks for a job requiring a longest processing time and to a second one of the instruction address registers for a second continuous period of M instruction clocks for a job requiring a second longest processing time, where N and M are both integers and N>M.   
     
     
       6. The digital signal processing apparatus according to claim 5 and further comprising two data address registers for storing and outputting data addresses for the current job and the previous job, respectively, which are cyclicly connected to the data memory by the switching means, one at a time, in accordance with the predetermined pattern of instruction clocks for cyclicly supplying data addresses for the current job and then the previous job to the computing block to enable job processing to be cyclicly switched between the current job and the previous job. 
     
     
       7. The digital signal processing apparatus according to claim 6 wherein the data address registers each have a separate input and an output and wherein the data memory includes an address generator which is cyclicly connected by the switching means in accordance with the predetermined pattern of instruction clocks between the output of one of the data address registers and then the output of another of the data address registers for cyclicly generating a new address and supplying the new address to the data memory and to the inputs of the data address registers as a reference address. 
     
     
       8. The digital signal processing apparatus according to claim 10 wherein the computing block has inputs and an output and further comprising computed data registers for separately storing and outputting job processing data for the current job and the previous job, respectively, and having separate inputs connected to the output of the computing block and separate outputs which are cyclicly connected, one at a time, by the switching means to one of the inputs of the computing block in accordance with the predetermined pattern of instruction clocks. 
     
     
       9. The digital signal processing apparatus according to claim 5 further comprising a coefficient memory and two coefficient address registers for separately storing and outputting coefficient addresses for the current job and the previous job, respectively, which are cyclicly connected to the coefficient memory by the switching means, one at a time, in accordance with the predetermined pattern of instruction clocks for cyclicly supplying coefficient addresses for the current job and then the previous job to the coefficient memory to enable job processing to be cyclicly switched between the current job and the previous job.