System for securing and electrically connecting a semiconductor chip to a substrate

Abstract

A system for securing and electrically connecting a semiconductor chip to a body of passive substrate. The semiconductor chip and the substrate are both provided with bonding pads or bonding areas. The bonding pads or areas are located so that when a chip is placed next to the substrate, at least some of the bonding pads on the chip are aligned with corresponding bonding areas on the substrate. Micro-pins in the shape of straight wires, stubs or loops are used to electrically connect some of the bonding pads on the chip to corresponding areas on the substrate thereby electrically connecting them and also securely bonding the chip to the substrate. In the preferred embodiment, epoxy is used to further strengthen the physical bonding between the chip and the substrate. The wicking action of the micro-pins reduces bridging of solder across adjacent micro-pins.

What is claimed is: 
     
       1. A semiconductor chip package comprising: a semiconductor die;   a substrate structure;   a first set of bonding pads on a first surface of the die;   a second set of bonding areas on a second surface of the substrate structure wherein the pads in the first set and areas in the second set are located such that when the first and second surfaces are placed adjacent each other, and for at least some of the areas on the second set, each of said at least some areas in the second set is aligned with a pad in the first set, said two aligned pad and area defining a corresponding pair; and   means for securing and electrically connecting at least some of the corresponding pairs, thereby securely bonding said semiconductor die to said structure,   wherein said securing and electrically connecting means includes an alloy and a plurality of elongated members for drawing the alloy towards predetermined locations on the bonding pads to reduce the probability of bridging of the alloy.   
     
     
       2. The package of claim 1, wherein said plurality of elongated members comprises pins, stubs or loops. 
     
     
       3. The package of claim 2, wherein said alloy comprises solder placed on top of at least some of the areas in the corresponding pairs and wherein said pins, stubs or loops are made of a material which adheres to solder. 
     
     
       4. The package of claim 3, wherein said material is non-oxidizing. 
     
     
       5. The package of claim 4, wherein said material is gold, silver, aluminum or copper. 
     
     
       6. The package of claim 5, wherein said material is gold and said solder is a lead/tin alloy of about 90% lead and 10% tin. 
     
     
       7. The package of claim 5, wherein said material is aluminum or copper and said solder is a tin/lead alloy of about 60% tin and 40% lead. 
     
     
       8. The package of claim 1, wherein said substrate is a circuit board of a chip-on-board or hybrid construction. 
     
     
       9. The package of claim 8, wherein said circuit board is made of ceramic, fiberglass, porcelain steel or aluminum. 
     
     
       10. The package of claim 1 further comprising a plurality of elongated conducting means on or in the structure for connecting the bonding areas in the second set to desired locations on or in the structure, wherein the spacing between individual conducting means is in the range of about two mils to three mils. 
     
     
       11. The package of claim 1 further comprising bonding means for securely attaching the semiconductor die to the substrate. 
     
     
       12. The package of claim 11, wherein said bonding means is epoxy. 
     
     
       13. The package of claim 1, said alloy including alignment means for facilitating the alignment of the corresponding first set of bonding pads. 
     
     
       14. The package of claim 13, said alignment means comprising a depression in said alloy in at least one of the second set of areas. 
     
     
       15. The package of claim 1, wherein the low temperature alloy is drawn towards a location on the substrate at or near one end of each elongated member. 
     
     
       16. The package of claim 1, wherein the spacing between adjacent bonding pads of the first set of bonding pads and the spacing between adjacent bonding pads in the second set do not exceed about two mils to three mils. 
     
     
       17. The package of claim 10, at least one of said plurality of elongated conducting means comprising alignment means for facilitating the alignment of the corresponding first set of bonding pads. 
     
     
       18. The package of claim 17, said alignment means comprising a depression in at least one of the plurality of elongated conducting means. 
     
     
       19. The package of claim 13, said alloy having a flattened top surface.