Digital data detecting and synchronizing circuit

Abstract

A circuit for detecting digital data has a data-changing point detecting circuit for detecting a changing point of the digital data at which a value indicative of the digital data is changed from value 1 to value 0, or value 0 to value 1; an asynchronous detecting circuit for judging whether or not the changing point is caused at a timing synchronized with the timing of the internal clock signal; an asynchronous counter for counting the number of asynchronizations; a synchronous signal generating counter for generating a synchronous signal by the internal clock signal; and a reset control circuit for controlling the timing of a reset operation of the synchronous signal generating counter in accordance with outputs of the data-changing point detecting circuit and the asynchronous counter. Another digital data detecting circuit and a method for detecting digital data are also shown.

What is claimed is: 
     
       1. A digital data detecting circuit for forming a receiving clock signal synchronized with every bit of digital data and detecting contents of the digital data, said digital data detecting circuit comprising: a synchronous signal generating counter, responsive to a reference clock signal, for generating the receiving clock signal sychronized with every bit of digital data;   a data-changing point detecting circuit for detecting a changing point of the digital data at which a value indicative of the digital data is changed from value 1 to value 0, or value 0 to value 1;   an asynchronous detecting circuit, responsive to the data-changing point detecting circuit and the synchronous signal generating counter, for detecting asyncroizations by judging whether or not said changing point occurs at the timing of the reference clock signal;   an asynchronous counter for counting the number of detected asynchronizations; and   a reset control circuit for controlling the timing of a reset operation of said synchronous signal generating counter in accordance with outputs of said data-changing point detecting circuit and said asynchronous counter.   
     
     
       2. A digital data detecting circuit as claimed in claim 1, which further comprises a masking circuit and wherein said reset control circuit controls said masking circuit to correct a nonzero timing of said changing point to a zero timing in accordance with the output of said asynchronous counter. 
     
     
       3. A digital data detecting circuit as claimed in claim 2, wherein said masking circuit comprises a positive masking circuit for correcting the timing of the changing point shifted in a positive shifting direction and a negative masking circuit for correcting the timing of the changing point shifted in a negative shifting direction. 
     
     
       4. A digital data detecting circuit for forming a receiving clock signal synchronized with every bit of digital data and detecting contents of the digital data, said digital data detecting circuit comprising: a synchronuous signal generating counter, responsive to a reference clock signal, for generating the receiving clock signal sychronized with every bit of digital data;   a data-changing point detecting circuit for detecting a changing point of the digital data at which a value indicative of the digital data is changed from value 1 to value 0, or value 0 to value 1;   a masking pattern control circuit, responsive to a signal from the synchronous signal generating counter, for determining a masking bit to be masked in accordance with a shift amount of the timing of the changing point; and   a masking circuit, responsive to the masking pattern control circuit, for masking a bit of an output of the synchronous signal generating counter when the changing point is detected by the data-changing point detecting circuit; and   a reset control circuit for controlling the timing of a reset operation of said synchronous signal generating counter based on an output of the masking circuit.   
     
     
       5. A digital data detecting circuit as claimed in claim 4, wherein the masking pattern control circuit generates one of a plurality of masking patterns for determining the masking bit in accordance with the shift amount of the timing of the changing point, and the operation of the masking circuit is controlled on the basis of the generated masking pattern. 
     
     
       6. A digital data detecting circuit for forming a receiving clock signal synchronized with every bit of digital data and detecting contents of the digital data, said digital data detecting circuit comprising: a synchronous signal generating counter, responsive to a reference clock signal, for generating a synchronous signal;   a changing point detecting circuit for detecting a changing point of the digital data at which a value indicative of the digital data is changed from value 1 to value 0, or value 0 to value 1, said changing point detecting circuit using a selectable pulse width for noise judgment and neglecting a noise having a pulse width equal to or less than said pulse width for noise judgment;   an synchronous frequency detecting circuit, responsive to an output of the changing point detecting circuit, for detecting asynchronizations occurring in a constant period and outputting a signal in accordance with the frequency of asynchronizations; and   a reset control circuit for controlling the timing of a reset operation of said synchronous signal generating counter in accordance with said output of the changing point detecting circuit and the signal output from said asynchronous frequency detecting circuit.   
     
     
       7. A digital data detecting circuit as claimed in claim 6, wherein the pulse width for noise judgment is selected in accordance with the frequency of asynchronization. 
     
     
       8. A method for forming a receiving clock signal synchronized with every bit of digital data and detecting contents of the digital data, said method comprising the steps of: detecting a changing point of the digital data at which a value indicative of the digital data is changed from value 1 to value 0, or value 0 to value 1;   detecting asychronizations in response to the detected changing point by judging whether or not said changing point occurs at the timing of a reference clock signal;   counting the number of detected asynchronizations; and   controlling the timing of a reset operation of a synchronous signal generating counter generating the receiving clock signal sychronized with every bit of digital data in accordance with the detected changing point and the detected number of asynchronizations.