Potentiometric oscillator with reset and test input

Abstract

A phase-lock loop circuit including a voltage-controlled oscillator for generating a clock signal. The voltage-controlled oscillator includes a plurality of multiplexers coupled in series. The signal generated by the last multiplexer in the series is used as a clock signal. Each of the multiplexers in the series has a select input. Either a first signal or a second signal propagates through the series of multiplexers, depending on a select signal applied to the select inputs of the multiplexers. The second signal is the first signal with a predetermined delay. A 3-input multiplexer is connected to the first and last multiplexers in the series to the form a ring oscillator. The first or second signals output by the last multiplexer in the series is sent to an input of the 3-input multiplexer, and a test signal is sent to a third input of the 3-input multiplexer. The 3-input multiplexer also receives the select signal and a test mode signal. If the test mode signal is asserted, the 3-input multiplexer propagates the test signal to the first multiplexer in the series. If the test mode is not asserted, the 3-input multiplexer propagates either the first or the second signals based on the select signal. The phase-lock loop circuit also includes a phase frequency detection circuit for generating a phase difference signal indicative of the phase difference between the clock signal and a reference signal, a filter for generating a control signal to the voltage-controlled oscillator in response to the phase difference signal, and a feedback divider for receiving the clock signal and for feeding back a divided clock signal to the phase frequency detection circuit.

We claim: 
     
       1. A voltage-controlled oscillator for generating a clock signal, said voltage-controlled oscillator comprising: a plurality of multiplexers coupled in series, said plurality of multiplexers including a first multiplexer and a last multiplexer, each of said plurality of multiplexers having a signal input, a select input, and a signal output, said signal input of each of said plurality of multiplexers except said first multiplexer being electrically coupled with said signal output of a previous multiplexer of said plurality of multiplexers for receiving one of a first and second input signal from said previous multiplexer, said second input signal being said first input signal with a predetermined delay, said signal output of each of said plurality of multiplexers except said last multiplexer being electrically coupled with said signal input of a next multiplexer of said plurality of multiplexers for propagating one of said first and second input signals to said next multiplexer in response to a select signal applied at said select input, said last multiplexer generating said one of said first and second input signals as an output signal in response to said select signal applied at its select input:   a test circuit for generating a test signal of predetermined logic level;   a 3-input multiplexer having first, second and third signal inputs, a select input, and a signal output, said first and second signal input of said 3-input multiplexer being electrically coupled with said signal output of said last multiplexer for receiving said output signal, said signal output of said 3-input multiplexer being electrically coupled with said signal input of said first multiplexer, wherein said plurality of multiplexers and said 3-input multiplexer form a ring oscillator, said 3-input multiplexer receiving said first and second input signals at said first and second signal inputs of said 3-input multiplexer from said last multiplexer of said plurality of multiplexers and receiving said test signal as a third input signal at said third signal input, said 3-input multiplexer propagating one of said first, second and third input signals to said first multiplexer of said plurality of multiplexers;   a selecting circuit electrically coupled with said select input of each of said plurality of multiplexers and said select input of said 3-input multiplexer for generating said select signal to select one of said first and second input signals, said selected input signal being propagated through said ring oscillator; and   a initiator electrically coupled with said 3-input multiplexer for generating an initiate signal to select said test signal to be generated at said signal output of said 3-input multiplexer, said initiate signal overriding said select signal such that said test signal propagates through said ring oscillator with said predetermined logic level.   
     
     
       2. A voltage-controlled oscillator according to claim 1, wherein said plurality of multiplexers and said 3-input multiplexer are constructed in current-mode logic ("CML") circuits such that each of said first input signal, said second input signal, and said select signal is accompanied by its complement signal. 
     
     
       3. A voltage-controlled oscillator according to claim 2, wherein said 3-input multiplexer comprises: first pair of emitter-coupled transistors of first conductive type for receiving said first input signal and its complement signal at its bases;   second pair of emitter-coupled transistors of said first conductive type for receiving said second input signal and its complement signals at its bases;   third pair of emitter-coupled transistors of said first conductive type electrically coupled with said first and second pairs, a first collector of said third pair being electrically coupled with the coupled emitters of said first pair and a second collector of said third pair being electrically coupled with the coupled emitters of said second pair, the bases of said third pair receiving said select signal and its complement signal for selecting for output a selected signal and its complement, said selected signal and its complement being one of said first input signal and its complement from said first pair and said second input signal and its complement from said second pair, only when said initiate signal is not active;   fourth pair of emitter-coupled transistors of said first conductive type for receiving said test signal and its complement signal at its bases;   fifth pair of emitter-coupled transistors of said first conductive type electrically coupled with said third and fourth pairs, a first collector of said fifth pair being electrically coupled with the coupled emitters of said third pair and a second collector of said fifth pair being electrically coupled with the coupled emitters of said fourth pair, the bases of said fifth pair receiving said initiate signal and its complement signal for selecting for output one of said selected signal and its complement from said third pair and said test signal and its complement from said fourth pair, said initiate signal overriding said select signal; and   current source transistor of said first conductive type having its collector electrically coupled with the emitters of said fifth pair at the collector.   
     
     
       4. A voltage-controlled oscillator according to claim 3, wherein said first conductive type is an n-p-n transistor. 
     
     
       5. A voltage-controlled oscillator according to claim 4, wherein said initiator selects said test signal automatically during power-on. 
     
     
       6. A phase-lock loop circuit for generating a clock signal in response to a reference signal, said phase-lock loop circuit comprising: phase frequency detector for determining a phase difference between said clock signal and said reference signal, said phase frequency detector generating a phase difference signal indicative of said phase difference;   a filter electrically coupled to said phase frequency detector for receiving said phase difference signal and for generating a control signal in response to said phase difference signal;   a feedback divider electrically coupled to said phase frequency detector for feeding back a divided clock signal from said clock signal to said phase frequency detector;   voltage-controlled oscillator electrically coupled with said filter for receiving said control signal and for generating said clock signal at a frequency responsive to said control signal, said voltage-controlled oscillator being electrically coupled with said feedback divider for transmitting said clock signal to said feedback divider, said voltage-controlled oscillator comprising:   a plurality of multiplexers coupled in series, said plurality of multiplexers including a first multiplexer and a last multiplexer, each of said plurality of multiplexers having a signal input, a select input, and a signal output, said signal input of each of said plurality of multiplexers except said first multiplexer being electrically coupled with said signal output of a previous multiplexer of said plurality of multiplexers for receiving one of a first and second input signal from said previous multiplexer, said second input signal being said first input signal with a predetermined delay, said signal output of each of said plurality of multiplexers except said last multiplexer being electrically coupled with said signal input of a next multiplexer of said plurality of multiplexers for propagating one of said first and second input signals to said next multiplexer in response to a select signal applied at said select input, said last multiplexer generating said one of said first and second input signals as an output signal in response to said select signal applied at its select input;   a test circuit for generating a test signal of predetermined logic level;   a 3-input multiplexer having first, second and third signal inputs, a select input, and a signal output, said first and second signal input of said 3-input multiplexer being electrically coupled with said signal output of said last multiplexer for receiving said output signal, said signal output of said 3-input multiplexer being electrically coupled with said signal input of said first multiplexer, wherein said plurality of multiplexers and said 3-input multiplexer form a ring oscillator, said 3-input multiplexer receiving said first and second input signals at said first and second signal inputs of said 3-input multiplexer from said last multiplexer of said plurality of multiplexers and receiving said test signal as a third input signal at said third signal input, said 3-input multiplexer propagating one of said first, second and third input to said first multiplexer of said plurality of multiplexers;   a selecting circuit electrically coupled with said select input of each of said plurality of multiplexers and said select input of said 3-input multiplexer for generating said select signal to select one of said first and second input signals, said selected input signal being propagated through said ring oscillator; and   an initiator electrically coupled with said 3-input multiplexer for generating an initiate signal to select said test signal to be generated at said signal output of said 3-input multiplexer, said initiate signal overriding said select signal such that said test signal propagates through said ring oscillator with said predetermined logic level.   
     
     
       7. A phase-lock loop circuit according to claim 6, wherein said plurality of multiplexers and said 3-input multiplexer are constructed in current-mode logic ("CML") circuits such that each of said first input signal, said second input signal and said select signal is accompanied by its complement signal. 
     
     
       8. A phase-lock loop circuit according to claim 7, wherein said 3-input multiplexer comprises: first pair of emitter-coupled transistors of first conductive type for receiving said first input signal and its complement signal at its bases;   second pair of emitter-coupled transistors of said first conductive type for receiving said second input signal and its complement signals at its bases;   third pair of emitter-coupled transistors of said first conductive type electrically coupled with said first and second pairs, a first collector of said third pair being electrically coupled with the coupled emitters of said first pair and a second collector of said third pair being electrically coupled with the coupled emitters of said second pair, the bases of said third pair receiving said select signal and its complement signal for selecting for output a selected signal and its complement, said selected signal and its complement being one of said first input signal and its complement from said first pair and said second input signal and its complement from said second pair, only when said initiate signal is not active;   fourth pair of emitter-coupled transistors of said first conductive type for receiving said test signal and its complement signal at its bases;   fifth pair of emitter-coupled transistors of said first conductive type electrically coupled with said third and fourth pairs, a first collector of said fifth pair being electrically coupled with the coupled emitters of said third pair and a second collector of said fifth pair being electrically coupled with the coupled emitters of said fourth pair, the bases of said fifth pair receiving said initiate signal and its complement signal for selecting for output one of said selected signal and its complement from said third pair and said test signal and its complement from said fourth pair, said initiate signal overriding said select signal; and   current source transistor of said first conductive type having its collector electrically coupled with the emitters of said fifth pair at the collector.   
     
     
       9. A phase-lock loop circuit according to claim 8, wherein said first conductive type is an n-p-n transistor. 
     
     
       10. A phase-lock loop circuit according to claim 9, wherein said initiator generates said initiated signal automatically during power-on said phase-lock loop circuit. 
     
     
       11. A phase-lock loop circuit with a test mode for generating a clock signal in response to a reference signal, said test mode causing the components of said phase-lock loop circuit to be tested, said phase-lock loop circuit comprising: phase frequency detector for receiving said reference signal and for determining a phase difference between said clock signal and said reference signal, said phase frequency detector generating a phase difference signal indicative of said phase difference;   a filter electrically coupled to said phase frequency detector for receiving said phase difference signal and for generating a control signal in response to said phase difference signal;   a feedback divider electrically coupled to said phase frequency detector for feeding back a divided clock signal from said clock signal to said phase frequency detector;   voltage-controlled oscillator electrically coupled with said filter for receiving said control signal and for generating said clock signal at a frequency responsive to said control signal, said voltage-controlled oscillator being electrically coupled with said feedback divider for transmitting said clock signal to said feedback divider, said voltage-controlled oscillator comprising:   a plurality of multiplexers coupled in series, said plurality of multiplexers including a first multiplexer and a last multiplexer, each of said plurality of multiplexers having a signal input, a select input, and a signal output, said signal input of each of said plurality of multiplexers except said first multiplexer being electrically coupled with said signal output of a previous multiplexer of said plurality of multiplexers for receiving one of a first and second input signal from said previous multiplexer, said second input signal being said first input signal with a predetermined delay, said signal output of each of said plurality of multiplexers except said last multiplexer being electrically coupled with said signal input of a next multiplexer of said plurality of multiplexers for propagating one of said first and second input signals to said next multiplexer in response to a select signal applied at said select input, said last multiplexer generating said one of said first and second input signals as an output signal in response to said select signal applied at its select input;   a 3-input multiplexer having first, second and third signal inputs, a select input, and signal output, said first and second signal input of said 3-input multiplexer being electrically coupled with said signal output of said last multiplexer for receiving said output signal, said signal output of said 3-input multiplexer being electrically connected with said signal input of said first multiplexer, wherein said plurality of multiplexers and said 3-input multiplexer form a ring oscillator, said 3-input multiplexer receiving said first and second input signals at said first and second signal inputs of said 3-input multiplexer from said last multiplexer of said plurality of multiplexers and receiving said reference signal as a third input signal at said third signal input, said 3-input multiplexer propagating one of said first, second and third input signals to said first multiplexer of said plurality of multiplexers;   a selecting circuit electrically coupled with said select input of each of said plurality of multiplexers and said select input of said 3-input multiplexer for generating said select signal to select one of said first and second input signals, said selected input signal being propagated through said ring oscillator; and   a test mode selecting circuit coupled to said 3-input multiplexer for receiving a test mode signal to select said reference signal for generation at said signal output of said 3-input multiplexer, said test mode signal overriding said select signal such that said reference signal propagates through said ring oscillator.   
     
     
       12. A phase-lock loop circuit with a test mode according to claim 11, further comprising inhibit means electrically connected with said phase frequency detector for inhibiting reception of said reference signal by said phase frequency detector to cause said voltage-controlled oscillator to slow down. 
     
     
       13. A phase-lock loop circuit according to claim 12, wherein said 3-input multiplexer comprises: first pair of emitter-coupled transistors of first conductive type for receiving said first input signal and its complement signal at its bases;   second pair of emitter-coupled transistors of said first conductive type for receiving said second input signal and its complement signals at its bases;   third pair of emitter-coupled transistors of said first conductive type electrically coupled with said first and second pairs, a first collector of said third pair being electrically coupled with the coupled emitters of said first pair and a second collector of said third pair being electrically coupled with the coupled emitters of said second pair, the bases of said third pair receiving said select signal and its complement signal for selecting for output a selected signal and its complement, said selected signal and its complement being one of said first input signal and its complement from said first pair and said second input signal and its complement from said second pair, only when said test mode signal is not active;   fourth pair of emitter-coupled transistors of said first conductive type for receiving said reference signal and its complement signal at its bases;   fifth pair of emitter-coupled transistors of said first conductive type electrically coupled with said third and fourth pairs, a first collector of said fifth pair being electrically coupled with the coupled emitters of said third pair and a second collector of said fifth pair being electrically coupled with the coupled emitters of said fourth pair, the bases of said fifth pair receiving said test mode signal and its complement signal for selecting for output said reference signal and its complement from said fourth pair, said test mode signal overriding said select signal; and   current source transistor having its collector electrically coupled with the emitters of said fifth pair at the collector.   
     
     
       14. A phase-lock loop circuit according to claim 13, wherein said first conductive type is an n-p-n conduction.