Image information control apparatus and display system

Abstract

An image information control apparatus includes a partial write detector having at least two types of memory units for detecting and storing addresses accessed to a VRAM in units of lines in a scanning direction, thereby repeating the detection and the storage at different cycles, a circuit for performing calculations to recognize partial write information from contents of each of the memory units, memory units for storing the respective calculation results, a circuit for comparing the memory contents to determine a size relationship between partial write areas, a partial write ID signal controller for controlling a partial write ID signal on the basis of the size relationship between partial write areas and externally outputting the signal, and a circuit for, even when partial writing is being executed, forcibly interrupting the partial writing in accordance with a state of an external refresh control signal, starting refresh, and restarting the partial writing in accordance with a partial write state and a change in state of the refresh control signal.

What is claimed is: 
     
       1. An image information control apparatus, for performing partial writing to a VRAM, said apparatus comprising: a partial write detector for detecting and storing accessed addresses of the VRAM in units of lines in a scanning direction, said detector comprising at least two memory units arranged so that, during one predetermined time period, one of the memory units is used in a detecting operation to detect new accessed-address information while another of the memory units is used to retain previously detected information and, during a succeeding time period, the functions of the memory units are switched so that the other of the memory units is used in the detecting operation while the one of the memory units is used to retain the information detected in the preceding time period;   means for performing calculations to recognize partial write information from contents of each of the two memory units;   further memory units for storing the respective calculation results;   means for comparing contents of the further memory units to determine a size relationship between partial write areas;   means for controlling a partial write signal on the basis of the size relationship between partial write areas and externally outputting the signal; and   means for forcibly interrupting partial writing, even during execution, in accordance with a state of an external refresh control signal, performing refresh, and resuming partial writing in accordance with a partial write state and a change in state of the refresh control signal.   
     
     
       2. An apparatus according to claim 1, wherein the partial write information detected in units of lines by said two memory units is identified as continuous line address groups in the scan line direction from the accessed address data, and said means for performing calculations calculates at least one of the number of addresses, a start line address, an end line address, the number of lines for each group, and a total number of accessed lines. 
     
     
       3. An apparatus according to claim 1, wherein only access to said VRAM performed during writing is rendered valid. 
     
     
       4. An apparatus according to claim 1, wherein when the size relationship between the partial write areas obtained from the partial write information is to be determined, a detection period (sampling period) of a memory unit having partial write information of a larger area is shorter than a storage period thereof. 
     
     
       5. An apparatus according to claim 1, wherein a cycle of determining the size relationship between the partial write areas obtained from the partial write information is synchronized with a cycle of said partial write detector for repeating detection and storage such that the cycles are integer multiples with respect to said two memory units, respectively. 
     
     
       6. An image information control apparatus according to claim 1, further comprising a display panel.   
     
     
       7. An apparatus according to claim 6, wherein the partial write information detected in units of lines by said two memory units is identified as continuous line address groups in the scan line direction from the accessed address data, and said means for performing calculations calculates at least one of the number of addresses, a start line address, an end line address, the number of lines for each group, and a total number of accessed lines. 
     
     
       8. A system according to claim 6, wherein only access to said VRAM performed during writing is rendered valid. 
     
     
       9. A system according to claim 6, wherein when the size relationship between the partial write areas obtained from the partial write information is to be determined, a detection period (sampling period) of a memory unit having partial write information of a larger area is shorter than a storage period thereof. 
     
     
       10. A system according to claim 6, wherein a cycle of determining the size relationship between the partial write areas obtained from the partial write information is synchronized with a cycle of said partial write detector for repeating detection and storage such that the cycles are integer multiples with respect to said two memory units, respectively. 
     
     
       11. An image information control method for controlling partial writing to a VRAM, said method comprising: detecting, during one predetermined time period, accessed VRAM line addresses in a scanning direction using one memory unit while retaining already detected data in another memory unit;   calculating partial rewrite information from the retained line address data;   storing the calculation results in additional memory units;   comparing contents of the additional memory units to recognize relative sizes of partial rewrite areas;   determining whether a number of the accessed line addresses exceeds a specified number; and   based on the result of the determination, interrupting partial rewriting even during execution thereof, and performing refresh scanning of an entire frame.