Sample and hold circuit being arranged for easily changing phases of shift clocks

Abstract

A sample and hold circuit is arranged to have a first shift register, a second shift register, a first group of sample and hold elements, a second group of sample and hold elements, and a phase switching circuit. The first shift register has a serial-in and parallel-out function and serves to shift an input sampling pulse in synchronization to the first shift clock. The second shift register has a serial-in and parallel-out function and serves to shift the input sampling pulse in a synchronous to a second shift clock being different from the first shift clock by a predetermined angle of phase. The first group of sample and hold elements serves to sample an analog signal in synchronization to an output from the first shift register. The second group of sample and hold elements serves to sample an analog signal in synchronization an output from the second shift register. The phase switching circuit serves to switch a phase relation between the first shift clock and the second shift clock in a manner so as to keep a predetermined phase angle between the first and the second shift clocks.

What is claimed is: 
     
       1. A driving circuit for a liquid crystal display panel including a plurality of pixel lines, each line arranged to have a plurality of pixels arranged in a horizontal manner, and pixels of odd lines and pixels of even lines being staggered relative to each other, comprising: a first sample and hold circuit for supplying analog signals to odd numbered pixels of each line of the liquid crystal display panel; and   a second sample and hold circuit for supplying analog signals to even numbered pixels of each line of the liquid display panel;   each of said first and second sample and hold circuits further comprising,   a first shift register including a plurality of serially connected stages and having a serial-in and parallel-out function and for shifting an input sampling pulse in synchronization to a first shift clock and outputting the shifted sampling pulse,   a second shift register including a plurality of serially connected stages and having a serial-in and parallel-out function and for shifting the input sampling pulse in synchronization to a second shift clock, said second shift clock being different from said first shift clock by a predetermined angle of phase,   a first group of sample and hold elements for sampling a first analog signal for odd numbered lines of the liquid crystal display in synchronization to outputs from respective stages of said first shift register,   a second group of sample and hold elements for sampling a second analog signal for even numbered lines of the liquid crystal display in synchronization to outputs from respective stages of said second shift register, and   a phase switching circuit for supplying said first shift register with said sampling pulse and said first shift clock and for supplying said second shift register with said sampling pulse and said second shift clock, said phase switching circuit further comprising,   means for switching a phase relation between said first shift clock and said second shift clock so as to have a difference therebetween of a predetermined phase angle, thereby permitting said first and second sample and hold element groups to reverse the sequence in which each sample and hold element receives a sampling of analog signals, said switching means being arranged to receive first and second original shift clocks, an original sampling pulse, a first control signal instructing an inversion of the display, and a second control signal designating the sample and hold circuit as either of said first and second sample and hold circuits, and to have   a first selector for selecting either the received first original shift clock or the reversal thereof as said first shift clock based on the received first and second control signals,   a second selector for selecting either the received second original shift clock or the reversal thereof based on the received first and second control signals,   a third selector for selecting either the received second original clock or the reversal thereof as said second shift clock based on the received second control signal, and   a flip-flop circuit connected to receive the input original sampling pulse and a clock selected by said second selector for outputting said sampling pulse in synchronization to said clock selected by said second selector.   
     
     
       2. A driving circuit as claimed in claim 1, wherein said first original shift clock is advanced or lagged in phase relative to said second original shift clock by a quarter period. 
     
     
       3. A driving circuit as claimed in claim 1, wherein said switching means switches the phases of the first and second shift clocks relative to each other by advancing or retarding one of said shift clocks relative to the other by a quarter period. 
     
     
       4. A driving circuit as claimed in claim 1, wherein said first and second shift register comprise bidirectional shift registers. 
     
     
       5. A driving circuit as claimed in claim 1, wherein said sample and hold elements of the first and second groups are alternately staggered and a pair of adjacent sample and hold elements are connected to receive outputs from the same stages of the two shift registers. 
     
     
       6. A driving circuit as claimed in claim 3, further including an output unit having a plurality of output circuits for supplying the analog signals held by respective sample and hold elements, each output circuit being connected to receive output signals of said adjacent sample and hold circuits and outputting one of the received analog signals in response to an input control signal.