Floating-point and fixed-point addition-subtraction assembly

Abstract

Apparatus for use in a floating-point and fixed-point adder-subtractor assembly. The apparatus includes a comparator and selector circuit disposed prior to an adder-subtracter for determining a larger and smaller operand prior to the addition and subtraction operation. The comparator and selector circuit inputs the larger operand into a first predetermined input of the adder-subtracter and the smaller operand into a second predetermined input of the adder-subtracter. Additionally, first and second selector circuits may be provided for multiplexing first and second fixed point data operands into the first and second inputs of the adder-subtracter, respectively. A shifter is provided for shifting at least one of the operands prior to inputting the operand into the adder-subtracter for selectively performing a position alignment. Accordingly, a simplified structure provides fixed-point and floating-point data addition-subtraction in a highly efficient manner.

What is claimed is: 
     
       1. A floating-point and fixed-point adder-subtractor assembly comprising: a comparator and selector circuit comparing a first operand including a first exponent and a first fraction with a second operand including a second exponent and a second fraction, respectively, for determining which of the first and second operands has a larger magnitude;   an exponent subtracter for calculating a difference between the first and second exponents;   a first barrel shifter for shifting one of the first and second fractions in an amount equal to the difference for a first position alignment of the first and second fractions;   a first adder-subtracter for adding-subtracting the first and second fractions for generating a third fraction after the first and second fractions are positioned-aligned by the first barrel shifter;   a first one-bit shifter for shifting the third fraction in an amount equal to or less than one bit for a first normalization;   a first selection circuit for selectively outputting a first fixed-point data or one of the first and second fractions supplied from the comparator and selector circuit;   a second selection circuit for selectively outputting a second fixed-point data or the other of the first and second fractions not supplied to the first selection circuit;   a second one-bit shifter for shifting the one of the first and second fractions supplied from the first selection circuit in an amount equal to the difference for a second position alignment of the first and second fractions;   a second adder-subtracter for adding-subtracting the first and second fractions for generating a fourth fraction after the first and second fractions are positioned-aligned by the second one-bit shifter, the second adder-subtracter adding-subtracting the first fixed-point data and second fixed-point data in a fixed-point adding-subtracting mode;   a second barrel shifter for shifting the fourth fraction in an amount corresponding to the fourth fraction for a second normalization;   a third selection circuit for selecting one of the outputs of the first one-bit shifter and second barrel-shifter; and   an exponent updater for generating a third exponent for the fourth fractions.   
     
     
       2. The floating-point and fixed-point adder-subtracter of claim 1 wherein the first adder-subtracter adds-subtracts a third fixed-point data and a fourth fixed-point data in the fixed-point adding-subtracting mode independently of the second adder-subtracter. 
     
     
       3. The floating-point and fixed-point adder-subtracter assembly of claim 2 wherein the comparator and selector circuit receives and passes the third and fourth fixed-point data. 
     
     
       4. An apparatus for use in a floating-point and fixed-point adder-subtractor assembly comprising: a first operand input supplying a first operand, the first operand including a first exponent and a first fraction;   a second operand input supplying a second operand, the second operand including a second exponent and a second fraction;   first and second fixed-point data inputs supplying first and second fixed-point data operands;   an adder-subtracter having first and second inputs and an output, the adder-subtracter for adding-subtracting operands;   comparator and selector circuit means, coupled to the first and second operand inputs, receiving the first and second operands, comparing the first fraction with the second fraction and comparing the first exponent with the second exponent for determining which of the first and second operands is the larger operand and which of the first and second operands is the smaller operand, for outputting the smaller operand on a first output and outputting the larger operand on a second output;   first selector means having a first input coupled to the first fixed-point data input for receiving the first fixed-point data operand, a second input coupled to the first output of the comparator and selector circuit means for receiving the smaller operand, and a first output for selectively outputting the first fixed-point data operand or the smaller operand to the first input of the adder-subtracter;   second selector means having a first input coupled to the second fixed-point data input for receiving the second fixed-point data operand, a second input coupled to the second output of the comparator and selector circuit means for receiving the larger operand, and a first output for selectively outputting the second fixed-point data operand or the larger operand to the second input of the adder-subtracter;   a shifter, coupled between one of the first and second inputs of the adder-subtracter and one of the first and second outputs of the comparator and selector circuit means, for selectively performing a position alignment, wherein the comparator and selector circuit is disposed prior to an adder-subtracter for determining a larger and smaller operand prior to the addition and subtraction operation and wherein first and second selector circuits allow the same adder-subtracter to be utilized for both fixed-point and floating-point operations, whereby an efficient structure is realized.