ECL gate having active pull-down transistor

Abstract

The present invention relates to a modified emitter coupled logic circuit which includes a differential logic stage and an emitter-follower output stage. An active pull-down circuit and a constant voltage source are included in the output stage of this circuit to allow the output of the circuit to switch from a high level to a low level at approximately the same speed as the output can switch from a low level to a high level. A particular embodiment of the present invention provides a constant voltage source comprising an operational amplifier, a reference potential generating circuit and a constant voltage signal adjusting circuit.

What is claimed is: 
     
       1. An integrated circuit comprising: a first transistor and a second transistor, each of said transistors having an emitter, a base and a collector, wherein said emitter of said first transistor and said emitter of said second transistor are coupled together, and wherein said base of said first transistor comprises a first node, and wherein said base of said second transistor comprises a second node;   a third transistor having an emitter, a base and a collector, wherein said base of said third transistor is coupled to said collector of said first transistor, and wherein said emitter of said third transistor comprises a third node characterized by a third node potential;   a first resistive element, said first resistive element being coupled to said collector of said second transistor and to said emitter of said third transistor;   a fourth transistor having an emitter, a base and a collector, wherein said emitter of said third transistor is coupled to said collector of said fourth transistor, and wherein said collector of said second transistor is coupled to said base of said fourth transistor;   a first reference potential;   a second resistive element coupled to said collector of said first transistor and to said first reference potential, wherein said collector of said third transistor is coupled to said first reference potential; and   a constant voltage source, said constant voltage source generating a constant voltage signal, wherein said constant voltage source is coupled to said emitter of said fourth transistor, and wherein said constant voltage source is regulated such that the time required for said third node potential to switch from a first level to a second level is substantially equal to the time required for said third node potential to switch from said second level to said first level.   
     
     
       2. The circuit of claim 1 further comprising a second reference potential coupled to said base of said first transistor. 
     
     
       3. The circuit of claim 1 further comprising a second reference potential coupled to said base of said second transistor. 
     
     
       4. The circuit of claim 1 further comprising a current source coupled to said emitters of said first and second transistors. 
     
     
       5. The circuit of claim 4 further comprising a fifth transistor, wherein said emitters of said first and second transistors are coupled to said current source through said fifth transistor. 
     
     
       6. The circuit of claim 1 wherein said first reference potential is ground. 
     
     
       7. The circuit of claim 1 further comprising a third resistive element having a first terminal and a second terminal, wherein said first terminal of said third resistive element is connected to said first reference potential, and wherein said collector of said third transistor is coupled to said second terminal of said third resistive element, and wherein said second resistive element is connected to said second terminal of said third resistive element. 
     
     
       8. The circuit of claim 1 wherein said constant voltage source comprises: a reference potential generating circuit generating a second reference potential;   an operational amplifier having a first input terminal and second input terminal, wherein said second reference potential is provided to said first input terminal, and said constant voltage signal is provided to said second input terminal of said operational amplifier, and wherein said operational amplifier generates a correction signal in response to said second reference potential and said constant voltage signal; and   a constant voltage signal adjustment circuit coupled to said operational amplifier, said operational amplifier providing said correction signal to said constant voltage adjustment circuit, whereby said constant voltage signal adjustment circuit adjusts said constant voltage signal in response to said correction signal.   
     
     
       9. The circuit of claim 8 wherein said reference potential generating circuit comprises: a fifth transistor and a sixth transistor, each of said transistors having an emitter, a base and a collector, wherein said emitter of said fifth transistor and said emitter of said sixth transistor are coupled together;   a seventh transistor having an emitter, a base and a collector, wherein said base of said seventh transistor is coupled to said collector of said fifth transistor, and wherein said collector of said seventh transistor is coupled to said first reference potential;   a third resistive element, said third resistive element being coupled to said collector of said sixth transistor and to said emitter of said seventh transistor;   a fourth resistive element having a first terminal and a second terminal, said first terminal of said fourth resistive element being coupled to said collector of said fifth transistor and to said base of said seventh transistor, and wherein said second terminal of said fourth resistive element is coupled to said first reference potential;   a current source; and   an eighth transistor having an emitter, a base and a collector, wherein said emitter of said seventh transistor is coupled to said collector of said eighth transistor, and wherein said collector of said sixth transistor is coupled to said base of said eighth transistor, wherein said emitter of said eighth transistor is coupled to said current source, and wherein said emitter of said eighth transistor generates said second reference potential.   
     
     
       10. The circuit of claim 8 wherein said reference potential generating circuit comprises: a third reference potential;   a fifth transistor having an emitter, a base and a collector, wherein said third reference potential is provided to said base of said fifth transistor;   a sixth transistor having an emitter, a base and a collector, wherein said collector of said fifth transistor is coupled to said base of said sixth transistor, and wherein said collector of said sixth transistor is coupled to said first reference potential;   a third resistive element having a first end and a second end, wherein said emitter of said sixth transistor is coupled to said first end of said third resistive element;   a fourth resistive element having a first terminal and a second terminal, said first terminal of said fourth resistive element being coupled to said collector of said fifth transistor and to said base of said sixth transistor, wherein said second terminal of said fourth resistive element is coupled to said first reference potential;   a current source; and   a seventh transistor having an emitter, a base and a collector, wherein said emitter of said sixth transistor is coupled to said collector of said seventh transistor, and wherein said base of said seventh transistor is coupled to said second end of said third resistive element, and wherein said emitter of said seventh transistor is coupled to said current source, and wherein said emitter of said seventh transistor provides said second reference potential.   
     
     
       11. The circuit of claim 8 wherein said constant voltage signal adjustment circuit comprises: a fifth transistor having an emitter, a base and a collector, wherein said operational amplifier provides said correction signal to said base of said fifth transistor causing said emitter of said fifth transistor to generate an emitter output signal;   a current mirror circuit coupled to said emitter of said fifth transistor;   a third resistive element coupled to said current mirror circuit, said current mirror circuit causing a current to flow through said third resistive element which is proportional to said emitter output signal; and   a sixth transistor having an emitter, a base and a collector, wherein said collector of said sixth transistor is coupled to one end of said third resistive element, said one end being coupled to said current mirror circuit, and wherein said base of said sixth transistor is coupled to another end of said third resistive element, and wherein said another end is coupled to said constant voltage source.   
     
     
       12. The circuit of claim 11 wherein said current mirror circuit comprises: a seventh transistor having an emitter, a base and a collector, wherein said base of said seventh transistor is coupled to said collector of said seventh transistor;   an eighth transistor having an emitter, a base and a collector, wherein said base of said eighth transistor is coupled to said base of said seventh transistor, and wherein said collector of said eighth transistor is coupled to said base of said sixth transistor; and   a fourth resistive element coupled to said emitter of said fifth transistor and to said collector of said seventh transistor.   
     
     
       13. The circuit of claim 11 further comprising a capacitor, wherein said collector of said sixth transistor is coupled to ground through said capacitor. 
     
     
       14. The circuit of claim 11 further comprising: a ninth transistor having an emitter, a base and a collector, wherein said collector of said ninth transistor is coupled to said base of said ninth transistor, and wherein said collector of said ninth transistor is coupled to ground; and   a fourth resistive element, wherein said collector of said sixth transistor is coupled to one end of said fourth resistive element, and wherein said emitter of said ninth transistor is coupled to another end of said fourth resistive element.   
     
     
       15. The circuit of claim 11 further comprising: a constant voltage signal line coupled to said base of said sixth transistor; and   a seventh transistor having an emitter, a base and a collector, wherein said collector of said seventh transistor is coupled to said emitter of said fourth transistor, and wherein said base of said seventh transistor is coupled to said constant voltage signal line.   
     
     
       16. The circuit of claim 15 further comprising a capacitor, wherein one terminal of said capacitor is coupled to said base of said seventh transistor and another terminal of said capacitor is coupled to said collector of said seventh transistor. 
     
     
       17. The circuit of claim 1 further comprising a temperature compensation circuit for compensating variations in transistor properties caused by changes in ambient temperature, wherein said temperature compensation circuit is coupled to said collector of said first transistor. 
     
     
       18. The circuit of claim 17 wherein said compensation circuit comprises: a first diode and a second diode, wherein said first diode is coupled in parallel to said second diode; and   a third resistive element, wherein a first end of said third resistive element is coupled in series to said first diode which is coupled in series to said second diode.   
     
     
       19. The circuit of claim 18 wherein a second end of said third resistive element is coupled to said collector of said first transistor, and wherein said first diode and said second diode are coupled to said collector of said second transistor. 
     
     
       20. The circuit of claim 1 further comprising: a first temperature compensation circuit comprising a diode and a third resistive element, wherein said first temperature compensation circuit is coupled to ground and to said collector of said first transistor; and   a second temperature compensation circuit comprising a fourth resistive element coupled in series to a second diode coupled in series to a third diode, wherein said fourth resistive element is coupled to said collector of said transistor of said first transistor, and wherein said third diode is coupled to said collector of said second transistor.   
     
     
       21. The circuit of claim 1 further comprising: a fifth transistor having an emitter, a base and a collector, wherein said collector of said first transistor is coupled to said collector of said fifth transistor, and wherein said emitter of said first transistor is coupled to said emitter of said fifth transistor;   a first logic input signal coupled to said base of said first transistor; and   a second logic input signal coupled to said base of said fifth transistor, wherein said first logic signal and said second logic signal are combined to produce a logic output signal at said collector of said fourth transistor, wherein said logic output signal represents a logical NOR operation between said first logic input signal and said second logic input signal.   
     
     
       22. The circuit of claim 1 further comprising a logic signal coupled to said base of said first transistor, wherein application of said logic signal to said base of said first transistor causes a logic output signal to appear at said collector of said fourth transistor, and wherein said logic output signal represents a logical NOT operation on said logic input signal. 
     
     
       23. The circuit of claim 1 further comprising: a second reference potential coupled to said base of said first transistor; and   a logic input signal coupled to said base of said second transistor.   
     
     
       24. The circuit of claim 5 further comprising: a second current source;   a sixth transistor having an emitter, a base and a collector, wherein said collector of said second transistor is coupled to said collector of said sixth transistor, and wherein said emitter of said sixth transistor is coupled to said emitter of said fifth transistor and to said current source;   a seventh transistor having an emitter, a base and a collector, wherein said emitter of said seventh transistor is coupled to said second current source;   a first logic input signal coupled to said base of said first transistor; and   a second logic input signal coupled to said base of said seventh transistor, wherein said first logic signal and said second logic signal are combined to produce a logic output signal at said collector of said fourth transistor, wherein said logic output signal represents a logical NAND operation between said first logic input signal and said second logic input signal.   
     
     
       25. A circuit comprising: a first differential logic circuit having an input branch and an output branch, said output branch having at least a first and a second output state;   an active circuit element; and   a constant voltage source coupled to said output branch of said differential logic circuit, said constant voltage source for supplying a constant voltage signal to said output branch of said differential logic circuit so that the time required for said output branch to switch from said first output state to said second output state is substantially equal to the time required for said output branch to switch from said second output state to said first output state, wherein said output branch of said differential logic circuit is coupled to said constant voltage source through said active circuit element.   
     
     
       26. The circuit of claim 25 wherein the constant voltage source comprises: a reference potential generator for generating a reference potential signal; and   a differential amplifier for comparing said reference potential signal with said constant voltage signal and generating a correction signal for adjusting said constant voltage signal.   
     
     
       27. The circuit of claim 26 wherein said differential amplifier is an operational amplifier. 
     
     
       28. The circuit of claim 26 wherein said reference potential generator comprises an emitter-coupled logic circuit. 
     
     
       29. The circuit of claim 25 wherein said output circuit comprises an emitter-follower circuit. 
     
     
       30. The circuit of claim 29 further comprising a second active circuit element which couples said emitter-follower circuit to ground. 
     
     
       31. The circuit of claim 25 wherein said input branch comprises an input active circuit element and said output branch comprises an output branch active circuit element, wherein said input active circuit element is coupled to said output branch active circuit element. 
     
     
       32. The circuit of claim 31 wherein said input active circuit element comprises a first bipolar transistor and said output branch active circuit element comprises a second bipolar transistor. 
     
     
       33. The circuit of claim 32 wherein each of said bipolar transistors comprises an emitter and wherein said emitter of said first bipolar transistor is coupled to said emitter of said second bipolar transistor. 
     
     
       34. The circuit of claim 33 further comprising a second differential logic circuit comprising an input branch and an output branch, wherein said second differential logic circuit is coupled to said constant voltage source. 
     
     
       35. The circuit of claim 34 wherein said input branch of said second differential logic circuit is coupled to said input branch of said first differential logic circuit. 
     
     
       36. The circuit of claim 34 wherein said output branch of said second differential logic circuit is coupled to said output branch of said first differential logic circuit. 
     
     
       37. The circuit of claim 33 wherein said input branch of said second differential logic circuit is coupled both to said input branch and to said output branch of said first differential logic circuit. 
     
     
       38. The circuit of claim 34 wherein said input branch of said first differential logic circuit is coupled to said output branch of said second differential logic circuit, and wherein said output branch of said first differential logic circuit is coupled to said input branch of said second differential logic circuit. 
     
     
       39. An integrated circuit comprising: a first transistor and a second transistor, each of said transistors having an emitter, a base and a collector, wherein said emitter of said first transistor and said emitter of said second transistor are coupled together, and wherein said bases of said first and second transistor are defined as a first input terminal and a second input terminal, respectively;   a third transistor having an emitter, a base and a collector, wherein said base of said third transistor is coupled to said collector of said first transistor, and wherein said emitter of said third transistor is defined as an output terminal;   a first resistive element, said first resistive element being coupled to said collector of said second transistor and to said emitter of said third transistor;   a fourth transistor having an emitter, a base and a collector, wherein said emitter of said third transistor is coupled to said collector of said fourth transistor, and wherein said collector of said second transistor is coupled to said base of said fourth transistor;   a first reference potential;   a second resistive element coupled to said collector of said first transistor and to said first reference potential, wherein said collector of said third transistor is coupled to said first reference potential; and   a constant voltage source, said constant voltage source generating a constant voltage signal, wherein said constant voltage source is coupled to said emitter of said fourth transistor, and wherein said constant voltage source is regulated such that the time required for said third transistor to switch from a substantially conducting state to a substantially non-conducting state is approximately equal to the time for said fourth transistor to switch from a substantially conducting state to a substantially non-conducting state.