Position detecting and time measuring device providing measurement finer than a clock signal period

Abstract

First absolute position detecting section generates an A.C. output signal having a phase electrically shifted in accordance with a position of a moving object, and samples a counted value of a counter circuit in response to an electrical phase change at a zero cross time point of the A.C. output signal, so as to output the sampled counted value of the counter circuit as absolute position data of the moving object. Second absolute position detecting section generates one or more delayed clock signals that are delayed from a clock signal on the basis of which the counter circuit counts up by an amount of time smaller than one period of the clock signal, and utilizes the one or more delayed clock signals to measure the zero cross time point of the A.C. output signal in accordance with a unit time smaller than the one period of the clock signal, so as to output, as the absolute position data, the measured time point after having been added to the sampled counted value.

What is claimed is: 
     
       1. A position detecting device which comprises: a first absolute position detecting means for generating an A.C. output signal having a phase electrically shifted in accordance with a position of a moving object, sampling a counted value of a counter circuit in response to an electrical phase change at a zero cross time point of the A.C. output signal, and outputting the sampled counted value of the counter circuit as absolute position data of the moving object, and   a second absolute position detecting means for generating one or more delayed clock signals delayed from a clock signal on the basis of which said counter circuit counts by an amount of time smaller than one period of the clock signal, for utilizing the one or more delayed clock signals to measure the zero cross time point of the A.C. output signal in accordance with a unit time smaller than the one period of the clock signal, and for outputting, as said absolute position data, the measured time point after having been added to said sampled counted value.   
     
     
       2. A position detecting device as defined in claim 1, in which said first absolute position detecting means comprises: clock oscillator means for generating a clock signal having a repetition of first and second level changes;   counter means that counts up in response to the first level change of the clock signal;   zero cross detecting means for detecting the zero cross time point of the A.C. output signal to output a predetermined trigger pulse;   latch pulse generator means for outputting a latch pulse in response to first detected one of said second level change since the trigger pulse has been inputted to the latch pulse generator means, and   holding means for holding a value being counted by said counter means when the latch pulse is input to the holding means, and in which   said second absolute position detecting means comprises:   delay means comprising a plurality of delay circuits connected in series with each other, each of said delay circuits outputting a delayed clock signal that is delayed from the clock signal by an amount of time smaller than one period of the clock signal, and   high-accuracy position detecting means for receiving the plurality of delayed clock signals from said delay means, and for performing a division of dividing the number of the delayed clock signals having a delay time smaller than the one period of the clock signal and also having said second level change of the clock signal prior to the zero cross time point of the A.C. output signal, by the number of said delayed clock signals having a delay time smaller than the one period of the clock signal, so that the high-accuracy position detecting means outputs, as said absolute position data, a result of the division after having been added to the sample counted value.   
     
     
       3. A position detecting device as defined in claim 2, in which said high-accuracy position detecting means comprises: a plurality of delayed latch pulse generators for receiving the plurality of delayed clock signals from said delay means, each of said delayed latch pulse generators outputting a delayed latch pulse in response to first detected one of said second level change, since the trigger pulse has been inputted to the delayed latch pulse generator;   pattern holding means for receiving a plurality of the delayed latch pulses from said delay latch pulse generators, detecting levels of the delayed latch pulses, and holding the detected levels as a level pattern comprising data indicative of the delayed latch pulses;   divisor and dividend detecting means for receiving the level pattern from said pattern holding means, and outputting, as said divisor, a number of the level patterns outputted during a time in which the level pattern changes from a first level to a second level and again to the first level and further outputting, as the dividend, the number of the level patterns outputted during the time in which the level pattern changes from the first level to the second level and again to the first level and currently having the first level; and   dividing means for performing a division between the divisor and the dividend, and outputting, as said absolute position data, a result of the division after having been added to said counted value.   
     
     
       4. A position detecting device as defined in claim 2, in which said delay means comprises a plurality of gate circuits. 
     
     
       5. A position detecting device as defined in claim 1, in which said absolute position detecting means is rotational position detecting means for detecting a rotational position of the moving object. 
     
     
       6. A position detecting device as defined in claim 1, in which said absolute position detecting means is linear position detecting means for detecting a linear position of the moving object. 
     
     
       7. A position detecting device as defined in claim 1 which comprises: difference calculating means for calculating a difference between a preceding value and a current value of said absolute position data outputted from said first and second absolute position detecting means at each sampling period;   pulse generating means for subtracting a predetermined allowance time from the sampling period to obtain a predetermined pulse generation time and generating, at an equal interval within the pulse generation time, a specific number of pulses which corresponds to the difference calculated by the difference calculating means, and   position data generating means for sequentially outputting, in response to the pulses provided from said pulse generating means, position data between the preceding values and current values of said absolute position data, in order to generate absolute position data without any slip-out.   
     
     
       8. A position detecting device as defined in claim 7 which forms incremental pulse on the basis of the absolute position data outputted from said position data generating means. 
     
     
       9. A position detecting device as defined in claim 1 wherein said second absolute position detecting means comprises: generating means for generating one or more delayed clock signals delayed from the clock signal on the basis of which said counter circuit counts by an amount of time smaller than one period of the clock signal;   means for utilizing the one or more delayed clock signals to measure the zero cross time point of the A.C. output signal in accordance with a unit time smaller than the one period of the clock signal; and   outputting means for outputting, as said absolute position data, the measured time point after having been added to said sampled counted value.   
     
     
       10. A position detecting device as defined in claim 1 wherein said second absolute position detecting means comprises: a plurality of serially connected delay circuits wherein each of said delay circuits outputs a delayed clock signal.   
     
     
       11. A position detecting device as defined in claim 1 wherein said second absolute position detecting means comprises: a plurality of delayed latch pulse generators wherein each of the delayed latch pulse generators receives a respective one of the one or more delayed clock signals and outputs a delayed latch pulse; and   pattern holding circuit for receiving the delayed latch pulses, detecting a level of the delayed latch pulses and generating a level pattern comprising data indicating the detected levels of the latch pulses.   
     
     
       12. A position detecting device as defined in claim 11 wherein said second absolute position detecting means further comprises: a divisor and dividend detecting circuit for receiving the level pattern and generating a divisor and dividend; and   a dividing circuit for performing a division between the divisor and dividend and outputting a result of the division;   an adding circuit wherein said result of the division is added to said counted value and outputting said absolute position data.   
     
     
       13. A time measuring device for detecting when a trigger pulse is inputted, which comprises: clock oscillator means for generating a clock signal having a repetition of first and second level changes;   counter means that counts up in response to the first level change of the clock signal;   latch pulse generator means for outputting a latch pulse in response to first detected one of said second level change since the trigger pulse has been inputted to the latch pulse generator means;   holding means for holding a value being counted by said counter means when the latch pulse is inputted to the holding means, and outputting the held value as a part of data indicating when the trigger pulse is inputted;   delay means comprising a plurality of delay circuits connected in series with each other, each of said delay circuits outputting a delayed clock signal that is delayed from the clock signal by an amount of time smaller than one period of the clock signal, and   time detecting means for receiving a plurality of the delayed clock signals from said delay means, and for performing a division of dividing the number of the delayed clock signals having a delay time smaller than one period of the clock signal and also having said second level change of the clock signal prior to input timing of the trigger pulse, by the number of said delayed clock signals having a delay time smaller than the one period of the clock signal, so that the time detecting means outputs, as the part of data indicating when the trigger pulse is inputted, a result of the division after having been added to the value held by said holding circuit.   
     
     
       14. A time measuring device as defined in claim 13, in which said time detecting means comprises: a plurality of delayed latch pulse generators for receiving the plurality of delayed clock signals from said delay means, each of said delayed latch pulse generators outputting a delayed latch pulse in response to first detected one of said second level change since the trigger pulse has been inputted to the respective latch pulse generator;   pattern holding means for receiving a plurality of the delayed latch pulses from said delayed latch pulse generators, detecting levels of the delayed latch pulses, and holding the detected levels as a level pattern of the delayed latch pulses;   divisor and dividend detecting means for receiving the level pattern from said pattern holding means, and outputting, as said divisor, the number of the level patterns outputted during a time in which the level pattern changes from a first level to a second level and again to the first level and further outputting, as the dividend, the number of the level patterns outputted during a time in which the level pattern changes from the first level to the second level and again to the first level and also currently having the first level; and   dividing means for performing a division between the divisor and the dividend, and outputting, as the part of data indicating when the trigger pulse is inputted, a result of the division after having been added to said value held by said holding means.   
     
     
       15. A time measuring device as defined in claim 13, in which said delay means comprises a plurality of gate circuits.