Read and write timing system for random access memory

Abstract

A differential latching inverter uses a pair of cross-coupled inverters having a skewed voltage transfer function to rapidly sense a differential signal on a pair of bit lines in a random access memory and provide high speed sensing during a read operation. The differential latching inverter may also include a pair of symmetrical transfer function output inverters and additional pull-up circuits to enhance high speed operation. The differential latching inverter may be used in a memory architecture having primary bit lines and signal bit lines, with a differential latching inverter being connected to each pair of signal bit lines. The primary bit lines and signal bit lines are coupled to one another during read and write operations and decoupled from one another otherwise. The read and write operations may be internally timed without the need for external clock pulses in response to a high speed address change detection system, and internal timing signals generated by delay ring segment buffers. A high speed, low power random access memory may thereby be provided.

That which is claimed is: 
     
       1. A system for timing a read operation in a memory comprising: means for initiating a read operation;   means for controlling a read operation in said memory in response to a plurality of control signals at a plurality of control inputs thereof;   a plurality of Delay Ring Segment Buffers (D-RSB), each of which includes an input and an output, said output replicating said input after a predetermined delay, each of said inputs of said D-RSBs being responsive to said initiating means, a respective one of said outputs being connected to a respective one of the control inputs of said controlling means, to thereby produce said plurality of control signals in a predetermined timing relationship for controlling the read operation; and   means for indicating that a read operation has successfully occurred, said plurality of D-RSBs being responsive to said indicating means, to deactivate said controlling means after a read operation has successfully occurred.   
     
     
       2. The timing system of claim 1 wherein said controlling means comprise at least one word decoder and at least one bit decoder. 
     
     
       3. The timing system of claim 2 wherein said controlling means further comprise at least one sensing means. 
     
     
       4. The timing system of claim 1 wherein said memory comprises an array of memory cells and a plurality of sensing means connected to said array of memory cells, for sensing binary data stored in a selected one of said cells, and wherein said indicating means comprises means for indicating that one of said sensing means has successfully sensed binary data stored in a selected one of said cells. 
     
     
       5. The timing system of claim 4 wherein said indicating means comprises an OR gate network having said plurality of inputs and an output, with a respective OR gate network input being connected to a respective one of said sensing means, said OR gate network output indicating that one of said sensing means has successfully sensed binary data stored in a selected one of said cells. 
     
     
       6. The timing system of claim 5 wherein said OR gate network comprises a single Complementary Logic Input Parallel (CLIP) OR gate having said plurality of inputs. 
     
     
       7. The timing system of claim 1 wherein said initiating means comprises address change detecting means. 
     
     
       8. The timing system of claim 4 wherein each of said sensing means comprises a Field Effect Transistor (FET) Differential Latching Inverter (DLI) circuit comprising: first and second complementary FET inverters, each of which is connected between said first and second reference voltages, and each of which includes an input and an output;   the FETs of each of said first and second complementary inverters producing an inverter transfer function which is skewed toward said second reference voltage; and   the input of said first inverter being connected to the output of said second inverter, and the input of said second inverter being connected to the output of said first inverter.   
     
     
       9. The timing system of claim 8 wherein said first and second complementary FET inverters each comprise at least one FET of first conductivity type and at least one FET of second conductivity type; the product of the square channel saturation current and the ratio of width to length of said at least one FET of said first conductivity type being substantially greater than the product of the square channel saturation current and the ratio of width to length of said at least one FET of said second conductivity type, to thereby produce said skewed inverter transfer function.   
     
     
       10. The timing system of claim 8: wherein said first complementary FET inverter comprises a first inverter FET of first conductivity type, and second and third inverter FETs of second conductivity type, the controlled electrodes of said first, second and third FETs being serially connected between said first and second reference voltages, the controlling electrodes of said first and second FETs being connected together to form the input of said first inverter;   wherein said second complementary FET inverter comprises a fourth inverter FET of first conductivity type, and fifth and sixth inverter FETs of second conductivity type, the controlled electrodes of said fourth, fifth and sixth FETs being serially connected between said first and second reference voltages, the controlling electrodes of said fourth and fifth FETs being connected together to form the input of said second inverter;   the controlling electrode of said third FET being connected between a controlled electrode of said fourth FET and a controlled electrode of one of said fifth and sixth FETs, the controlling electrode of said sixth FET being connected between an controlled electrode of said first FET and a controlled electrode of one of said second and third FETs;   the product of the square channel saturation current and the ratio of channel width to length of the second, third, fifth and sixth inverter FETs being substantially greater than the product of the square channel saturation current and the ratio of channel width to length of said first and fourth inverter FETs, to produce said skewed inverter transfer function.   
     
     
       11. A system for timing a read operation in a Random Access Memory (RAM) comprising: means for initiating a write operation;   means for controlling a write operation in said RAM in response to a plurality of control signals thereto at a plurality of control inputs thereof;   a plurality of Delay Ring Segment Buffers (D-RSB), each of which includes an input and an output, said output replicating said input after a predetermined delay, each of said inputs of said D-RSBs being responsive to said initiating means, a respective one of said outputs being connected to a respective one of the control inputs of said controlling means, to thereby produce said plurality of control signals in a predetermined timing relationship for controlling the write operation; and   means for indicating that a write operation has successfully occurred, said plurality of D-RSBs being responsive to said indicating means, to deactivate said controlling means after a write operation has successfully occurred.   
     
     
       12. The timing system of claim 11 wherein said controlling means comprises at least one word decoder and at least one bit decoder. 
     
     
       13. The timing system of claim 11 further comprising: means for sensing data written in said RAM during a write operation, said indicating means being responsive to said sensing means, for indicating that a write operation has successfully occurred.   
     
     
       14. The timing system of claim 13 wherein said memory comprises an array of memory cells and a plurality of sensing means connected to said array of memory cells, for sensing binary data stored in a selected one of said cells, and wherein said indicating means comprises means for indicating that one of said sensing means has successfully sensed binary data stored in a selected one of said cells. 
     
     
       15. The timing system of claim 14 wherein said indicating means comprises an OR gate network having said plurality of inputs and an output, with a respective OR gate network input being connected to a respective one of said sensing means, said OR gate network output indicating that one of said sensing means has successfully sensed binary data stored in a selected one of said cells. 
     
     
       16. The timing system of claim 15 wherein said OR gate network comprises a single, Complementary Logic Input Parallel (CLIP) OR gate having said plurality of inputs. 
     
     
       17. The timing system of claim 11 wherein said initiating means comprises address change detecting means. 
     
     
       18. The timing system of claim 13 wherein each of said sensing means comprises a Field Effect Transistor (FET) Differential Latching Inverter (DLI) circuit comprising: first and second complementary FET inverters, each of which is connected between said first and second reference voltages, and each of which includes an input and an output;   the FETs of each of said first and second complementary inverters producing an inverter transfer function which is skewed toward said second reference voltage; and   the input of said first inverter being connected to the output of said second inverter, and the input of said second inverter being connected to the output of said first inverter.   
     
     
       19. The timing system of claim 18 wherein said first and second complementary FET inverters each comprise at least one FET of first conductivity type and at least one FET of second conductivity type; the product of the square channel saturation current and the ratio of width to length of said at least one FET of said first conductivity type being substantially greater than the product of the square channel saturation current and the ratio of width to length of said at least one FET of said second conductivity type, to thereby produce said skewed inverter transfer function.   
     
     
       20. The timing system of claim 18: wherein said first complementary FET inverter comprises a first inverter FET of first conductivity type, and second and third inverter FETs of second conductivity type, the controlled electrodes of said first, second and third FETs being serially connected between said first and second reference voltages, the controlling electrodes of said first and second FETs being connected together to form the input of said first inverter;   wherein said second complementary FET inverter comprises a fourth inverter FET of first conductivity type, and fifth and sixth inverter FETs of second conductivity type, the controlled electrodes of said fourth, fifth and sixth FETs being serially connected between said first and second reference voltages, the controlling electrodes of said fourth and fifth FETs being connected together to form the input of said second inverter;   the controlling electrode of said third FET being connected between a controlled electrode of said fourth FET and a controlled electrode of one of said fifth and sixth FETs, the controlling electrode of said sixth FET being connected between an controlled electrode of said first FET and a controlled electrode of one of said second and third FETs;   the product of the square channel saturation current and the ratio of channel width to length of the second, third, fifth and sixth inverter FETs being substantially greater than the product of the square channel saturation current and the ratio of channel width to length of said first and fourth inverter FETs, to produce said skewed inverter transfer function.