Method of making a dynamic random access memory device

Abstract

Disclosed is a dynamic random access memory device (DRAM) having an increased cell capacitance and simplified manufacturing method thereof. The storage electrode the capacitor of the DRAM is connected to a semiconductor substrate through an opening formed in an insulating layer, and has a structure having an outer peripheral wall portion with a laterally extending bottom on the insulating layer and an inner central pillar portion including a hole of a certain depth within the opening in the center of the outer peripheral wall portion. Thus, cell capacitance is greatly increased within a limited unit cell area, its reliability is enhanced, and the manufacturing process is distinctly simplified.

What is claimed is: 
     
       1. A method of manufacturing a capacitor electrode in a semiconductor device comprising the steps of: (a) forming an insulating layer on a semiconductor substrate having at least one transistor with a source region;   (b) forming a first conductive layer on said insulating layer;   (c) forming at least one first material pattern on said first conductive layer corresponding in location to said source region;   (d) etching said at least one first material pattern, said first conductive layer, and said insulating layer to form a first opening which exposes said source region;   (e) forming a second conductive layer over said first conductive layer having said opening formed therethrough, said second conductive layer covering a sidewall of said first opening and said source region to obtain a second opening having a smaller diameter than said first opening;   (f) etching back said second conductive layer to expose said at least one etched first material pattern; and   (g) removing said at least one etched first material pattern to obtain said capacitor electrode.   
     
     
       2. A method of manufacturing a capacitor electrode as claimed in claim 1, wherein said steps of forming said first and second conductive layers comprises forming first and second polycrystalline silicon layers, respectively. 
     
     
       3. A method of manufacturing a capacitor electrode as claimed in claim 1, wherein said step of forming at least one first material pattern comprises the steps of forming a first material layer on said first conductive layer and patterning said first material layer by photolithography. 
     
     
       4. A method of manufacturing a capacitor electrode as claimed in claim 1, wherein said step of forming at least one first material pattern comprises the steps of forming a compound material layer on said first conductive layer and patterning said compound material layer by photolithography. 
     
     
       5. A method of manufacturing a capacitor electrode as claimed in claim 1, further comprising a step of forming a second material layer on said insulating layer, prior to forming said first conductive layer. 
     
     
       6. A method of manufacturing a capacitor electrode as claimed in claim 5, further comprising a step of etching back said second material layer formed on said insulating layer after said step of removing said at least one etched first material pattern, thereby leaving a lower surface portion of said capacitor electrode spaced away from said insulating layer. 
     
     
       7. A method of manufacturing a capacitor electrode as claimed in claim 1, wherein said step of forming said second conductive layer causes said second opening to be formed.