Quick recovery AC coupling circuit

Abstract

A quick recovery AC coupling circuit has a coupling capacitor stage that generates an output DC-biased AC signal by capacitively coupling an input DC-biased AC signal generated by a source stage. The output DC-biased AC signal is biased by a biasing stage. The quick recovery AC coupling circuit utilizes an emitter follower which is biased at its emitter by an active device in both the source stage and the biasing stage to maintain the bias voltage across the coupling capacitor stage when the quick recovery AC coupling circuit is powered off and when a high-input impedance device is connected to receive the output DC-biased AC signal.

What is claimed is: 
     
       1. A quick-recovery AC coupling circuit for maintaining a bias voltage across a coupling capacitor when the circuit is powered off, the circuit comprising: a coupling capacitor stage that generates an output DC-biased AC signal at an output node by receiving an output DC bias voltage at a bias node and by capacitively coupling an input DC-biased AC signal at an input node to the output node;   a low-output impedance source stage that generates the input DC-biased AC signal at the input node to the coupling capacitor stage in response to an externally-generated AC signal and that prevents a first current from flowing from the coupling capacitor stage into the source stage when the circuit is powered off; and   a biasing stage that generates the output DC-bias voltage at the bias node and that prevents a second current from flowing from the coupling capacitor stage into the biasing stage when the circuit is powered off,   whereby when a high-input impedance device is connected to the output node and when the circuit is powered off, current cannot flow into or out of the coupling capacitor stage, thereby maintaining the bias voltage across the coupling capacitor stage.   
     
     
       2. The circuit of claim 1 wherein the coupling capacitor stage comprises: a capacitor connected between the input node and the output node; and   a resistor connected between the output node and the bias node.   
     
     
       3. The circuit of claim 2 wherein the source stage comprises: a first output substage that generates the input DC-biased AC signal in response to an intermediate DC-biased AC signal when the circuit is powered on and that prevents the first current from flowing from the coupling capacitor stage into the first output substage when the circuit is powered off;   a first DC bias substage that generates a signal DC bias voltage that sets the DC bias voltage for the intermediate DC-biased AC signal when the circuit is powered on; and   an AC signal substage that generates the intermediate DC-biased AC signal by combining the externally-generated AC signal and the signal DC bias voltage.   
     
     
       4. The circuit of claim 3 wherein the biasing stage means comprises: a second output substage that generates the output DC bias voltage in response to an intermediate bias voltage when the circuit is powered on and that prevents the second current from flowing from coupling capacitor stage into second output stage when the circuit is powered down; and   a second DC bias substage that generates the intermediate bias voltage when the circuit is powered on.   
     
     
       5. The circuit of claim 3 wherein the first output substage comprises: an emitter-follower transistor having its emitter connected to the input node, its base connected to the intermediate DC-biased AC signal, and its collector connected to a power supply; and   a current sink transistor having its emitter connected to ground, its base connected to a current mirror voltage, and its collector connected to the input node.   
     
     
       6. The circuit of claim 4 wherein the second output substage comprises: an emitter-follower transistor having its emitter connected to the bias node, its base connected to the intermediate DC voltage, and its collector connected to a power supply; and   a current sink transistor having its emitter connected to ground, its base connected to a current mirror voltage, and its collector connected to the bias node.   
     
     
       7. The circuit of claim 3 wherein the first output substage comprises: an source-follower transistor having its source connected to the input node, its gate connected to the intermediate DC-biased AC signal, and its drain connected to a power supply; and   a current sink transistor having its source connected to ground, its gate connected to a current mirror voltage, and its drain connected to the input node.   
     
     
       8. The circuit of claim 4 wherein the second output substage comprises: an source-follower transistor having its source connected to the bias node, its gate connected to the intermediate DC voltage, and its drain connected to a power supply; and   a current sink transistor having its source connected to ground, its gate connected to a current mirror voltage, and its drain connected to the bias node.