Address selective emulation routine pointer address mapping system

Abstract

An instruction mapping system comprises an instruction mapping circuit, a central processing unit (CPU), a data cache, and a memory. The address outputs of the CPU are coupled to a first address bus, while the address inputs of the data cache and memory are coupled to a second address bus. The instruction mapping circuit's address inputs are coupled to the first address bus, and the instruction mapping circuit's outputs are coupled to the second address bus. The CPU sends a pointer address via the first address bus to the instruction mapping circuit. The instruction mapping circuit determines whether the pointer address indicates that the next source instruction is within the subset of most frequently executed source instructions. If so, the instruction mapping circuit maps the pointer address to an address within the data cache. If not, the pointer address is routed through the instruction mapping circuit unchanged. The pointer address is next routed to the data cache and to the RAM via the second address bus. If the pointer address was mapped to a data cache address, the data cache outputs the pointer to the next emulation routine on the data bus. If the pointer address was not mapped to a data cache address, the pointer to the next emulation routine is output on the data bus at the data outputs of the memory. The present invention also includes a method for manufacturing an instruction mapping system.

What is claimed is: 
     
       1. An address selective address mapping system for a host computer system having a central processing unit (CPU) having data inputs and address outputs, and a memory having address inputs and data outputs, said CPU and said memory coupled to a data bus, the address selective address mapping system for selectively mapping a memory address storing a pointer to an emulation routine to a cache address, the address selective address mapping system comprising: a cache having address inputs, data inputs, and data outputs, for storing a plurality of pointers, each pointer corresponding to an emulation routine, the data inputs and data outputs of said cache coupled to said data bus;   an instruction mapping circuit having inputs and outputs for receiving and selectively translating the memory address into a corresponding cache address, the inputs of said instruction mapping circuit coupled to the address outputs of said CPU and the outputs of said instruction mapping circuit coupled to the address inputs of said memory and the address inputs of said cache, wherein said instruction mapping circuit further comprises: a decoder having inputs and an output for controlling whether an address received from said CPU is subject to being translated to a cache address by determining whether the address received corresponds to an address at which a pointer to an emulation routine for a source instruction within a source instruction set is stored, the inputs of said decoder coupled to receive an address signal from said CPU;   an address translation circuit having inputs and outputs for determining whether the address received corresponds to a source instruction that has a corresponding pointer to an emulation routine stored in said cache, the inputs of said address translation circuit coupled to receive the address signal from said CPU, wherein said address translation circuit further comprises: a programmable logic means having inputs, data outputs, and a control output for recognizing whether the address signal corresponds to a source instruction within the subset of most-frequently used source instructions within a source instruction set, for mapping the address signal to a corresponding cache address and for determining whether the cache address is valid, the inputs of said programmable logic means coupled to receive the address signal from said CPU; and   a bit substitution means having a first set of inputs, a second set of inputs, a control input, and a plurality of outputs, for selectively routing one from the group of the address signal and a mapped address signal, and conjoining a plurality of bits to form the mapped address signal, the first set of inputs coupled to the outputs of said programmable logic means, the second set of inputs coupled to receive the address signal from said CPU, the control input coupled to the control output of said programmable logic means;     and   an address selection means having a control input, first data inputs, second data inputs and outputs, said address selection means selectively outputting the signals from the first data inputs and the second data inputs, the control input of said address selection means coupled to the output of said decoder, the first data inputs coupled to the outputs of said address translation circuit, the second data inputs coupled to receive the address signal from said CPU, and the outputs of said address selection means coupled to the address inputs of said cache and the address inputs of said memory.