Integrated circuit for protecting internal circuitry from high voltage input test signals

Abstract

A semiconductor integrated circuit protected against a high voltage testing signal is provided. The integrated circuit includes a first-stage input circuit, a discriminating circuit, a power suppuly circuit and a connecting circuit. The input ends of the-input circuit and the discriminating circuit are connected to one preselected external terminal. The discriminating circuit renders a testing circuit drive signal active to activate when a testing instruction signal higher than an ordinary input signal voltage is applied to the external terminal. When the testing circuit drive signal is active, the power supply circuit disconnects at least one of the positive and negative poles of the power source having polarity opposite to that of the testing instruction signal from the input circuit, and the connecting circuit connects one of the positive and negative poles of the power source having the same polarity as that of the testing instruction signal to the output end of the input circuit.

What is claimed is: 
     
       1. A semiconductor integrated circuit, comprising: a circuit having first and second power source connecting ends through which a power source is supplied to said circuit, a first end connected to one preselected external terminal of said semiconductor integrated circuit, and a second end;   a discriminating circuit for providing a testing circuit drive signal for testing said semiconductor integrated circuit when a testing instruction signal higher than an ordinary input signal voltage by a predetermined voltage or more is applied to the external terminal;   a power supply circuit, connected to the testing circuit drive signal from the discriminating circuit, for connecting the positive and negative poles of said power source to said first and second power source connecting ends of said circuit, respectively, when the testing circuit drive signal is not active, but for disconnecting at least one of said positive and negative poles of said power source having polarity opposite to that of the testing instruction signal from said circuit when the testing circuit drive signal is active; and   a connecting circuit, connected to the testing circuit drive signal from the discriminating circuit, for connecting one of said positive and negative poles of said power source having the same polarity as that of the testing instruction signal to the second end of said circuit when the testing circuit drive signal is active.   
     
     
       2. A semiconductor integrated circuit as claimed in claim 1, wherein said positive pole of said power source is connected to said first power source connecting end of said circuit while said negative pole of said power source is connected to said second power source connecting end by way of said power supply circuit, and the testing instruction signal is active when said testing instruction signal has positive polarity whereas the testing circuit drive signal is active when said testing circuit drive signal has positive polarity. 
     
     
       3. A semiconductor integrated circuit as claimed in claim 2, wherein said circuit is a CMOS inverter comprising a P-channel MOS transistor and an N-channel MOS transistor, and said first power source connecting end is provided on a P-channel MOS transistor side of said CMOS inverter while said second power source connecting end is provided on an N-channel MOS transistor side of said CMOS inverter, and said power supply circuit is a P-channel MOS transistor which receives, at the gate thereof, the testing circuit drive signal while said connecting circuit is an N-channel MOS transistor which receives, at the gate thereof, the testing drive signal. 
     
     
       4. A semiconductor integrated circuit as claimed in claim 2, further comprising an inverter for inverting the testing circuit drive signal and providing as an output an inverted testing circuit drive signal, and wherein said circuit is a CMOS inverter comprising a P-channel MOS transistor and an N-channel MOS transistor, and said first power source connecting end is provided on a P-channel MOS transistor side of said CMOS inverter while said second power source connecting end is provided on an N-channel MOS transistor side of said CMOS inverter, and said power supply circuit is an N-channel MOS transistor which receives, at the gate thereof, the inverted testing circuit drive signal while said connecting circuit is a P-channel MOS transistor which receives, at the gate thereof, the inverted testing circuit drive signal. 
     
     
       5. A semiconductor integrated circuit as claimed in claim 2, further comprising an inverter for inverting the testing circuit drive signal and providing as an output an inverted testing circuit drive signal, and wherein said circuit includes first and second N-channel MOS transistors connected in series and said first power source connecting end is provided on a first N-channel MOS transistor side while said second power source connecting end is provided on a second N-channel MOS transistor side, and said power supply circuit is an N-channel MOS transistor which receives, at the gate thereof, the inverted testing circuit drive signal while said connecting circuit includes a first NAND circuit having an output end connected to the gate of said first N-channel MOS transistor, an input end to which a first internal signal is applied and another input end to which the output of said inverter is applied, and a second NAND circuit having an output end connected to the gate of said second N-channel MOS transistor, an input end to which a second internal signal is applied and another input end to which the output of said inverter is applied.