Heterojunction bipolar transistor

Abstract

Process for producing a transistor, particularly a heterojunction bipolar transistor, of the type comprising the known stages consisting in producing layers forming the collector, base and emitter, as well as collector, base and emitter ohmic contacts. The emitter producing stage consists in depositing, on the base layer, two superposed layers making up the emitter, the first of which is a thin layer made up of a first material having a large energy gap, and the second made up of a second material also having a high energy gap. The base ohmic contact is deposited on the first layer of the emitter. The invention also relates to the transistors obtained.

We claim: 
     
       1. Transistor comprising layers forming collector, base and emitter, and collector, base and emitter ohmic contacts, wherein: the emitter is made up of two layers of semiconductor material of a first type of conductivity superposed on the base layer: a first thin layer made up of a first material having a large energy gap and a second layer made up of a second material also having a large energy gap;   the base is made up of a semiconductor material of a second type of conductivity;   the collector is made up of a semiconductor material of the first type of conductivity; and   the base ohmic contact is deposited on the first thin layer making up the emitter.   
     
     
       2. The transistor of claim 1 wherein the energy gap of the second layer is smaller or equal to that of the first thin layer. 
     
     
       3. The transistor of claim 1 wherein for a npn transistor, the energy discontinuity between the valence band of GaAs and the valence band of the material for the first thin layer is greater than the energy discontinuity between the valence band of GaAs and the valence band of the for the second layer, whereas the energy discontinuity between the conduction band of GaAs and the conduction band of the material for the first thin layer is smaller than the energy discontinuity between the conduction band of GaAs and the conduction band of the material for the second layer. 
     
     
       4. The transistor of claim 1 wherein for a pnp transistor, the energy discontinuity between the valence band of GaAs and the valence band of the material for the first thin layer is smaller than the energy discontinuity between the valence band of GaAs and the valence band of the material for the second layer, whereas the energy discontinuity between the conduction band of GaAs and the conduction band of the material for the first thin layer is greater than the energy discontinuity between the conduction band of GaAs and the conduction band of the material for the second layer. 
     
     
       5. The transistor of claim 1 wherein the material used for the first thin layer forming the emitter has greater resistance to a chosen etching agent than the material used for the second layer forming the emitter. 
     
     
       6. The transistor of claim 1 wherein for a npn transistor, the materials making up the two layers of the emitter are chosen from the following pairs: GaInP for the first thin layer and GaAlAs for the second layer;   GaP for the first thin layer and GaAlAs or GaInP for the second layer;   InP for the first thin layer and AlInAs for the second layer.   
     
     
       7. The transistor of claim 1 wherein for a pnp transistor, the materials making up the two layers of the emitter are chosen from the following pairs: GaInP for the second layer and GaAlAs for the first thin layer;   GaP for the second layer and GaAlAs or GaInP for the first thin layer;   InP for the second layer and AlInAs for the first thin layer.   
     
     
       8. The transistor of claim 1 wherein for a npn transistor, the first thin layer is in InP whereas the second layer is in AlInAs. 
     
     
       9. The transistor of claim 1 wherein for a pnp transistor, the first thin layer is in AlInAs whereas the second layer is in InP. 
     
     
       10. The transistor of claim 1 wherein it comprises two etchings revealing, respectively, the first thin layer of the emitter and a collector contact layer. 
     
     
       11. The transistor of claim 1 wherein it comprises: on a substrate, a heavily doped layer of a first type of conductivity forming the collector contact layer;   on the collector contact layer, a lightly doped layer of the first type of conductivity forming the collector layer;   on the collector layer, a very heavily doped layer of the second type of conductivity forming the base layer;   on the base layer, a thin layer of the first type of conductivity in a first material having a wide energy gap, forming the first thin emitter layer;   on the first emitter layer, a second layer made up of a second material also having a high energy gap, forming the second emitter layer; and   on the second emitter layer, a heavily doped layer of the first type of conductivity forming the emitter contact layer.   
     
     
       12. The transistor of claim 1 wherein the thickness of the first thin layer making up the emitter is between 10 and 60 nm, preferably between 20 and 45 nm, very advantageously in the order of 30 nm. 
     
     
       13. The transistor of claim 1 wherein the first thin layer making up the emitter is doped to a level in the range 10 16  -10 17  cm -3 . 
     
     
       14. The transistor of claim 1 wherein the second layer making up the emitter is formed from Ga 1-x  Al x  As. 
     
     
       15. The transistor of claim 1 wherein the first thin layer making up the emitter is formed from GaInP. 
     
     
       16. The transistor of claim 1 wherein the collector layer is produced in GaAs, GaAlAs or GaInP. 
     
     
       17. The transistor of claim 1 wherein the base layer is in GaAs, GaAlAs or GaInAs. 
     
     
       18. The transistor of claim 1 wherein ohmic contacts are deposited respectively on the emitter contact and collector contact layers. 
     
     
       19. The transistor of claim 1 wherein the base ohmic contact is a diffusing contact. 
     
     
       20. The transistor of claim 1 wherein the base ohmic contact is produced in AuMn. 
     
     
       21. The transistor of claim 1 wherein it is produced using self-aligned technology. 
     
     
       22. Transistor comprising: a semiconductor substrate;   a semiconductor collector contact layer of a first type of conductivity, epitaxed on said substrate;   a semiconductor collector layer of the first type of conductivity epitaxed on said semiconductor collector contact layer;   a semiconductor base layer of a second type of conductivity epitaxed on said semiconductor collector layer;   a first semiconductor layer of the first type of conductivity epitaxed on said semiconductor base layer;   a second semiconductor layer of the first type of conductivity epitaxed on said first semiconductor layer, said first semiconductor layer and second semiconductor layer forming in combination an emitter layer;   a semiconductor emitter contact layer of the first type of conductivity epitaxed on said second semiconductor layer;   a collector ohmic contact deposited on said semiconductor collector contact layer;   an emitter ohmic contact deposited on said semiconductor emitter contact layer; and   a diffusing ohmic contact deposited on the first layer making up the emitter.