Microprocessor based systems providing simulated low voltage conditions for testing reset circuits

Abstract

A microprocessor system having two microprocessors, each of which has its own reset circuit, and a circuit being provided which detects under-voltage in the system supply voltage, each of said microprocessors having circuitry associated with it for inducing a simulated low voltage condition on the reset circuit of the other microprocessor to test said under-voltage detection circuit and to measure the resulting reset period generated.

We claim: 
     
       1. A microprocessor-controlled system, comprising: a first microprocessor;   means for establishing a supply voltage for said microprocessor; and   a reset circuit coupled to said microprocessor for holding the microprocessor in an inoperative reset condition;   the reset circuit incorporating: a reset line coupled to said microprocessor;   a low-voltage detection means for receiving said microprocessor supply voltage and producing a reset output signal level on said reset line if said microprocessor supply voltage falls below a predetermined level;   a timing means for holding said detected reset output signal level on said reset line for a specified reset period after said low-voltage detection means has indicated a presence of said supply voltage at an acceptable level; and   means for generating a simulated low voltage signal applied to said low-voltage detection means to force said reset circuit, and hence the microprocessor, into said reset condition, for testing purposes; and   a second microprocessor coupled to said first microprocessor for the mutual exchange of information, each of said first and second microprocessors having its own reset circuit associated with it and each having a simulated low voltage signal generating means for inducing a simulated low voltage signal applied to said low-voltage detection means of said reset circuit associated with the other one of said first and second microprocessors.     
     
     
       2. A microprocessor-controlled system according to claim 1, wherein the second microprocessor is coupled to said first microprocessor for the mutual exchange of information to ensure that either one of said first and second microprocessors will control said system by itself if the other microprocessor fails. 
     
     
       3. A microprocessor-controlled system according to claim 1 including a timing means for measuring the duration of said reset period of that one of said microprocessors which has been forced into said reset condition by the application thereto by the other microprocessor of said simulated low voltage condition, in order to test that the measured duration is within acceptable limits. 
     
     
       4. A microprocessor-controlled system according to claim 1, wherein said simulated low voltage condition inducing means is separate from said microprocessors. 
     
     
       5. A microprocessor-controlled system according to claim 1, wherein said first microprocessor is one of a plurality of microprocessors coupled together for the mutual exchange of information; each of said plurality of microprocessors having its own reset circuit associated with it, at least some of said plurality of microprocessors having respective simulated low voltage condition inducing means for inducing a simulated low voltage condition at said low-voltage detection means of respective reset circuits associated with other of said plurality of microprocessors. 
     
     
       6. A microprocessor-controlled system according to claim 15, including a timing means for measuring the duration of said reset period of any one of said microprocessors which has been forced into said reset condition by the application thereto of said simulated low voltage condition for determining if the measured duration of said reset period is within acceptable limits. 
     
     
       7. A microprocessor-controlled system according to claim 15, wherein said simulated low-voltage condition inducing means is separate from all of said microprocessors. 
     
     
       8. A microprocessor-controlled system which comprises a plurality of microprocessors coupled together for the mutual exchange of information, means for establishing a supply voltage for said plurality of microprocessors, each of said plurality of microprocessors having its own reset circuit associated with it for holding that microprocessor in an inoperative reset condition, each reset circuit incorporating a reset line coupled to that microprocessor, a low-voltage detection means for receiving said microprocessor supply voltage and for producing a reset signal level on said reset line if said microprocessor supply voltage falls below a predetermined level, a timing means for holding said reset output signal level on said reset line for a specified reset period after said low-voltage detection means has indicated a presence of said supply voltage at an acceptable level, and a device which is separate from all said microprocessors and which includes means for inducing a simulated low voltage condition on said low-voltage detection means of all microprocessors to force said reset circuits, and hence all said microprocessors, into said reset condition for testing purposes.