Thin film transistor which prevents generation of hot carriers

Abstract

A semiconductor transistor device comprises a gate electrode disposed over an insulating surface, a spacer element located at the end of the gate electrode, a gate insulating film covering the gate electrode, a first diffusion region spaced apart from one end of the gate electrode, separated therefrom by the gate insulating film and by the spacer element which reduces the electric field between the gate and first diffusion region, the first diffusion region extending vertically above the gate insulating film, and a second diffusion region disposed above the gate insulating film having one end spaced from the first diffusion vertically extending region.

I claim: 
     
       1. A semiconductor transistor device comprising: (a) a gate electrode disposed over an insulating surface;   (b) a gate insulating film covering said gate electrode;   (c) a first diffusion region spaced apart from one end of said gate electrode, and separated from said gate electrode by said gate insulating film, the first diffusion region extending vertically above said gate insulating film;   (d) a spacer element located at the one end of said gate electrode and covered by said gate insulating film, said spacer element and gate insulation films determining the distance between said gate electrode and first diffusion region, for reducing an electric field between said gate electrode and said first diffusion region; and,   (e) a second diffusion region disposed above said gate insulating film and having one end spaced from said first diffusion region.   
     
     
       2. A semiconductor device of claim 1 wherein said spacer element is in contact with said gate electrode one end. 
     
     
       3. A semiconductor transistor device comprising: (a) a gate electrode disposed over an insulating surface;   (b) a gate insulating film covering said gate electrode;   (c) a semiconductor thin film disposed over said insulating surface, and said gate electrode, and separated therefrom by said gate insulating film;   (d) a first diffusion region in said semiconductor thin film spaced apart from one end of said gate electrode, and separated from said gate electrode by said gate insulating film, the first diffusion region extending vertically above said gate insulating film;   (e) a spacer element located at one end of said gate electrode and said first diffusion region which determines with said gate insulating film the distance between sid first diffusion region and said gate electrode for reducing an electric field between said gate electrode and said first diffusion region; and,   (f) a second diffusion region in said semiconductor thin film disposed above said gate insulating film and having one end spaced from said first diffusion region.   
     
     
       4. A semiconductor device of claim 3 wherein said spacer element is covered by said gate insulating film. 
     
     
       5. A semiconductor device of claim 3 wherein said spacer element is in contact with said gate electrode one end. 
     
     
       6. A semiconductor transistor device comprising: a gate electrode disposed over an insulating surface;   a first diffusion region spaced apart from one end of said gate electrode;   means located between said first diffusion region and said gate electrode for reducing the electrical field between said electrode one end and said first diffusion region;   a gate insulating film covering said gate electrode; and   a second diffusion layer disposed over said gate insulating film, extending towards a vertically extending portion of said first diffusion region.   
     
     
       7. The semiconductor transistor of claim 6 wherein said gate insulating film covers said means for reducing the electric field. 
     
     
       8. The semiconductor transistor of claim 6 wherein said means for reducing the electric field is in contact with said gate electrode one end. 
     
     
       9. A semiconductor transistor device comprising: a gate electrode disposed over an insulating surface;   a first diffusion region spaced apart from one end of said gate electrode forming a drain region;   a gate insulating film covering said gate electrode;   a spacer element located between said first diffusion region and the one end of said gate electrode so that a distance between said first diffusion region and the one end of said gate electrode is substantially determined by said spacer element and said gate insulating film; and,   a second diffusion region disposed over said gate insulating film, extending towards a vertically extending portion of said first diffusion region forming a source.   
     
     
       10. The semiconductor transistor of claim 6 wherein said gate insulating film covers said means for reducing the electric field. 
     
     
       11. The semiconductor transistor of claim 6 wherein said means for reducing the electric field is in contact with said gate electrode one end. 
     
     
       12. A semiconductor transistor device comprising: (a) a gate electrode disposed over an insulating surface;   (b) a gate insulating film covering said gate electrode;   (c) a semiconducting film disposed over said insulating surface and said gate electrode and separated from said gate electrode by said gate insulating film;   (d) a drain formed in a first region of said semiconductor thin film spaced apart from one end of said gate electrode by said gate insulating film, extending to an area over said gate insulating film;   (e) a spacer element located between said drain region and gate electrode, which determines the distance between said drain and gate electrode, for reducing an electric field between said drain and gate electrode; and,   (f) a source formed in a second region of said semiconducting film located above said gate electrode and spaced from said drain region.   
     
     
       13. The semiconductor transistor device of claim 12 wherein said insulating film covers said spacer element. 
     
     
       14. The semiconductor transistor device of claim 13 wherein said spacer element abuts one end of said gate electrode.