Memory control device

Abstract

A memory control device adaptable to various demands and using a standard DRAM. A memory interface for outputting an address of the memory and controllably reading and writing is connected to the memory. A plurality of input and output ports are connected to the memory interface through a local bus. A host interface is connected to the memory interface through the local bus. A refresh control refreshes the memory through the memory interface. An arbitration structure arbitrates the required access to memory between the refresh control means, the input and output ports and the host interface.

What is claimed is: 
     
       1. A memory control device for controlling a dynamic memory that has a local bus, comprising: a memory interface, connected to said memory and to at least one external device, for controlling access to said memory so that all communication with said memory is provided through said memory interface;   a plurality of input and output ports coupled to said memory through said memory interface and the local bus;   refresh control means coupled to said memory through said memory interface for refreshing said memory;   arbitration means, connected to said memory interface, said input and output ports and said refresh control means, for arbitrating memory access requests from said refresh control means and said input and output ports on the basis of an access priority; and   means for adjusting the access priority of said refresh control means.   
     
     
       2. A memory control device as in claim 1, further comprising a host interface coupled to said memory through said memory interface and said local bus, wherein said arbitration means arbitrates memory access requests from said host interface, said refresh control means and any of said input and output ports. 
     
     
       3. A memory control device as claimed in claim 2, wherein the input and output ports and host interface comprise: a start address register for registering a starting address for access to said memory;   means for storing a size of an area of said memory to be accessed, a location of said area defined by said starting address;   an offset register for registering an offset of a column address used when moving from a low address access to a subsequent lower address access;   means for adding said offset to the column address on completing said access of a low address in said area of said memory.   
     
     
       4. A memory control device as claimed in claim 3, wherein said adding means for an input and output port is comprised of one input and output port common to all the input and output ports. 
     
     
       5. A device as in claim 2 wherein said host interface transforms image data from an interlace mode to a non-interlace mode by reading alternate rasters. 
     
     
       6. A memory control device as in claim 2, wherein said host interface operates in one of a random access mode, a page access mode, a direct memory access mode with the control device functioning in a master status, and a direct memory access mode with the control device functioning in a slave status. 
     
     
       7. A device as in claim 2, wherein said host interface controls operation in a random access mode in which an address of the memory is received through one of said input and output ports. 
     
     
       8. A memory control device as in claim 2, wherein said host interface controls operation in a page access mode in which a start address is received and incremented until a column end is reached, where a column number is automatically increased. 
     
     
       9. A memory control device as in claim 2, wherein said host interface further comprises address generation means, including: a line number register for storing a number of rasters in a vertical direction of an area to be addressed;   a pixel number register for storing a number of pixels in an horizontal direction of said area to be addressed; and   an offset register for storing a change of coordinates in the horizontal direction.   
     
     
       10. A device as in claim 9, wherein said offset register resets said change of coordinates stored in said offset register each time one raster is accessed. 
     
     
       11. A memory control device as claimed in claim 1, wherein each said input and output port includes input and output buffer means for temporarily storing input and output data. 
     
     
       12. A memory control device as claimed in claim 11, wherein said input and output buffer means comprise: a first buffer for storing data output from said memory;   a second buffer for storing data to input to said memory;   a third buffer for storing input and output data; and   switching means for connecting an output of said first buffer to an input of said second buffer, and connecting an output of said second buffer to an input of said third buffer for connecting an output of said third buffer to one of said input and output port and an output from the second buffer.   
     
     
       13. A memory control device as claimed in claim 12, wherein said third buffer includes: a plurality of registers for storing bit strings of 1 byte; and   byte selection means connected to an output of the third buffer for selecting one of said registers.   
     
     
       14. A memory control device as claimed in claim 13, wherein said bit selection means is set for selectively outputting 1 bit from one of said plurality of registers. 
     
     
       15. A memory control device as in claim 1 wherein one of said input and output ports is solely for control signals. 
     
     
       16. A memory control device as in claim 1, wherein said memory interface compresses data stored in said memory which comprises an comprising an image by controlling a reading of said memory so that only a partial amount of said data comprising said image will be read from said memory. 
     
     
       17. A device as in claim 16 wherein said contraction is carried out in a horizontal direction by intermittently reading pixels. 
     
     
       18. A device as in claim 16 wherein said contraction is carried out in a vertical direction by intermittently reading rasters. 
     
     
       19. A memory control device as in claim 1, wherein said access priority controlling means includes a refresh counter for counting the number of times said memory needs refreshing and the number of times that a memory access request from said refresh control means is not accepted by said arbitration means, with an access priority of said refresh control means being based on a count in said counter. 
     
     
       20. A memory control device as in claim 1, wherein said memory interface expands data stored in said memory which comprises an image by controlling a reading of said memory so that a partial amount of said data comprising said image will be repeatedly read from said memory. 
     
     
       21. A memory control device as in claim 20, wherein said memory interface controls a reading of said memory so as a pixel or raster is read multiple times when data is expanded. 
     
     
       22. A memory control device for controlling a dynamic memory comprising: a memory interface for connecting said memory to external devices, thereby controlling access to said memory;   a plurality of input and output ports coupled to said memory through said memory interface and a local bus;   refresh control means coupled to said memory through said memory interface for refreshing said memory;   arbitration means, connected to said memory interface, input and output ports and refresh control means, for arbitrating memory access requests from said refresh control means and said plurality of input and output ports on the basis of an access priority; and   a refresh counter for controllably adjusting the access priority of said refresh control means by counting the number of times said memory needs refreshing and the number of times that a memory access request from said refresh control means is not accepted by said arbitration means, with an access priority of said refresh control means being based on a count in said counter.