Input/output circuit having the input buffer circuit being connected in parallel with two transistors with the same polarity

Abstract

An input terminal is connected commonly with a first transistor gate and drain and a second transistor source having the same polarity with the first transistor. A first transistor source is connected to a voltage source. A second transistor gate is connected to the voltage source through a variable voltage source. A second transistor drain terminal is used as a current output terminal, and an input terminal is used as a voltage output terminal. The input circuit is capable of obtaining a current gain approximating "1" while input impedance variation due to input signal variation maintain suppressed smaller.

What is claimed is: 
     
       1. An input/output circuit for inputting signals through a transmission line, the input/output circuit comprising: an output buffer circuit for outputting signals into the transmission line; and   an input buffer circuit for inputting signals from the transmission line;   the input buffer circuit having: an input terminal that is a voltage output terminal of the input buffer circuit, the input terminal being connected to the transmission line;     a first transistor having a drain termianl and a gate termianl connected to the input terminal; a second transistor having a source terminal connected to the input terminal, the second transistir having the same channel conductivity type polarity with the first transistor; and   a current output termianl connected to a drain termianl of the second transistor.     
     
     
       2. An input buffer circuit connected to an output buffer circuit through a transmission line, the input buffer circuit comprising: an input terminal that is a voltage output terminal of the input buffer circuit, the input terminal being connected to the transmission line;   a first transistor having a drain terminal and a gate terminal connected to the input terminal;   a second transistor having a source terminal connected to the input terminal, the second transistor having the same channel conductivity type polarity with the first transistor; and   a current output terminal connected to a drain terminal of the second transistor.   
     
     
       3. An input buffer circuit as claimed in claim 2, the input buffer circuit further comprising; a bias voltage source included between the source terminal of the first transistor and the gate terminal of the second transistor. 
     
     
       4. An input buffer circuit as claimed in claim 3, wherein the bias voltage source comprise: a first current supply circuit for supplying a current responsive to a current flowing into the second transistor to the source terminal of the first transistor, and   a second current supply circuit for supplying a current to the first current supply circuit.   
     
     
       5. An input buffer circuit as claimed in claim 3, wherein the bias current source comprises: a first current supply circuit for supplying a current responsive to a current responsive to a current flowing into the second transistor to the source terminal of the first transistor;   a potential setting means for setting the input terminal potential to a predetermined value; and   a second current supply circuit for supplying a current to the first current supply circuit depending on a difference between a potential set by the potential setting means and a potential corresponding to a potential of input terminal.   
     
     
       6. An input buffer circuit as claimed in claim 5, wherein a voltage difference between a first voltage source connected to the source terminal of the first transistor and a second voltage source connected to the drain terminal of the second transistor is voltage-divided to set a set potential by the potential setting means. 
     
     
       7. An input buffer circuit as claimed in claim 6, wherein the first voltage source connected to the source terminal of the first transistor and the second voltage source connected to the drain terminal of the second transistor are connected to each other through a first resistance having a predetermined value and a second resistance having a predetermined value which are connected in series with each other, and a set potential by the potential setting means is obtained from a connecting point of the first resistance and the second resistance. 
     
     
       8. An input buffer circuit as claimed in claim 5, wherein the second current supply circuit extracts the input terminal potential from the first current supply circuit. 
     
     
       9. An input buffer circuit as claimed in claim 2, wherein the first and second transistors are formed of NMOSFETs. 
     
     
       10. An input buffer circuit as claimed in claim 2, wherein the first and second transistors are formed of PMOSFETs. 
     
     
       11. An input buffer circuit as claimed in claim 2, wherein said input signals are logical values corresponding to binary digital signals. 
     
     
       12. An input buffer circuit as claimed in claim 2, wherein said first transistor and said second transistor are composed so that a size of said first transistor may be about equal to a size of said second transistor. 
     
     
       13. An input buffer circuit as claimed in claim 2, wherein said transmission line is a connection line between IC's, and said transmission line has a designated specific impedance. 
     
     
       14. An input buffer circuit as claimed in claim 2, wherein said input buffer circuit obtains impedance matching for said transmission line by causing bias current to flow between said first transistor and said second transistor. 
     
     
       15. An input buffer circuit connected to an output buffer circuit through a transmission line, the input buffer circuit comprising: an input terminal that is a voltage output terminal of the input buffer circuit, the input terminal connected to the transmission line;   a first transistor having a drain terminal and a gate terminal connected to the input terminal;   a second transistor having a source terminal connected to the input terminal, the second transistor having the same channel conductivity type polarity with the first transistor;   a first current circuit for supplying a current depending on a current flowing into the first transistor;   a second current circuit for supplying a current depending on a current flowing into the second transistor; and   a current output terminal for outputting a current flowing into the first and second current circuits.   
     
     
       16. An input buffer circuit as claimed in claim 15, the input buffer circuit further comprising; a bias current source included between the source terminal of the first transistor and the gate terminal of the second transistor. 
     
     
       17. An input buffer circuit as claimed in claim 16, wherein the bias current source comprise: a first current supply circuit for supplying a current depending on a current flowing into the second transistor to the source terminal of the first transistor; and   a second current supplying circuit for supplying a current to the first current supply circuit.   
     
     
       18. An input buffer circuit as claimed in claim 16, wherein the bias current source comprises: a first current supply circuit for supplying a current depending on a current flowing into the second transistor to the source terminal of the first transistor;   a potential setting means for setting a potential of the input terminal to a predetermined value; and   a second current supply circuit for supplying to the first current supply circuit a current depending on a difference between a potential set by the potential setting means and a potential of the input terminal.   
     
     
       19. An input buffer circuit as claimed in claim 18, wherein a voltage difference between a potential at the source terminal-side of the first transistor and a potential at the drain terminal-side of the second transistor is voltage-divided to set a potential by the potential setting means. 
     
     
       20. An input buffer circuit as claimed in claim 19, wherein a potential at the first transistor source terminal-side and the second transistor drain terminal-side are connected each other through a first resistance having a predetermined value and a second resistance having a predetermined value which are connected in series with each other, and a set potential by the potential setting means is obtained from a connecting point of the first resistance and the second resistance. 
     
     
       21. An input buffer circuit as claimed in claim 18, wherein the second current supply circuit extracts the input terminal potential from the first current supply circuit. 
     
     
       22. An input buffer circuit as claimed in claim 15, wherein the first and second transistors are formed of NMOSFETs. 
     
     
       23. An input buffer circuit as claimed in claim 15, wherein the first and second transistors are formed of PMOSFETs.