Semiconductor device having stable breakdown voltage in wiring area

Abstract

A semiconductor device having stable breakdown voltage in wiring area. The semiconductor has a first conducting type semiconductor substrate with a plurality of second conducting type first semiconductor regions formed on one part of the surface of the first conducting type semiconductor substrate. A first conducting type high density diffused second semiconductor region is formed on one part of the surface within the second conducting type first semiconductor region. A gate electrode material extends across one part of the surface of the first conducting type semiconductor substrate, where one part of the surface of the first conducting type high density diffused second semiconductor region and the second conducting type first semiconductor region are not formed. An insulating film covers the gate electrode material and a metal source wiring is connected to the first conducting type high density diffused second semiconductor region and the second conducting type first semiconductor region. A metal gate wiring is connected to one part of the surface of the gate electrode material through an open section provided in the insulating film, and second conducting type third semiconductor regions are formed as a plurality of partitions on the surface of the first conducting type semiconductor substrate on the lower part of the metal gate wiring. In the semiconductor device, the second conducting type third semiconductor region is positioned to approach the limit reached by a depletion layer extending from the second conducting type third semiconductor region toward the first conducting type semiconductor substrate.

What is claimed is: 
     
       1. A semiconductor device having stable breakdown voltage in a wiring area, comprising: a first conducting type semiconductor substrate (21 and 22) having a major surface;   a plurality of second conducting type first semiconductor regions (27) embedded into the major surface of said semiconductor substrate (21,22);   a plurality of first conducting type high density diffused second semiconductor regions (28) embedded within each of said second conducting type first semiconductor regions (27);   a first insulating film (25) formed on said first semiconductor regions (27) and said semiconductor substrate (2, 22);   a gate electrode material (26) formed on said first insulating film (25) and formed over adjacent second semiconductor regions (28), said gate electrode material (26) not being in contact with each of said first conducting type high density diffused second semiconductor regions (28) and not being in contact with said second conducting type first semiconductor regions (27);   a second insulating film (29) which covers said gate electrode material (26);   metal source wiring (211) connected to each of said first conducting type high density diffused second semiconductor regions (28) and connected to each of said second conducting type first semiconductor regions (27);   a plurality of second conducting type third semiconductor regions (24) embedded into the major surface of said semiconductor substrate (21, 22), the thickness of said third semiconductor region being substantially equal to the thickness of said second conducting type first semiconductor regions (27), said insulating film (29) also covering a portion of said second conducting type third semiconductor region (24) and covering a portion of the major surface between each adjacent said second type third semiconductor regions (24); said second conducting type third semiconductor regions (24) being connected electrically to said metal source wiring (211);   metal gate wiring (23) formed on said insulating film (29) and formed over said second conducting type third semiconductor region (24), and connected to said gate electrode material through open sections provided in said insulating film (29) at a point along the major surface of the semiconductor substrate between adjacent said second conducting type third semiconductor regions; and   wherein a diffusion depth of said second conducting type third semiconductor regions (24) is substantially equal to the diffusion depth of said second conducting type first semiconductor regions (27), and said first conducting type high density diffused second semiconductor regions (28) are not formed in said second conducting type third semiconductor regions (24).   
     
     
       2. A semiconductor device as claimed in claim 1, wherein said metal gate wiring is connected electrically to the gate electrode material through said open section in the insulating film between each of said second conducting type third semiconductor regions on the semiconductor substrate. 
     
     
       3. A semiconductor device as claimed in claim 1, wherein a spacing between said second conducting type third semiconductor regions and said second conducting type first semiconductor regions is the same as a spacing between a pair of said second conducting type first semiconductor regions which are adjacent to each other. 
     
     
       4. A semiconductor device as claimed in claim 1, wherein a width (Ls) of any of said second conducting type third semiconductor regions is substantially equal to a width of any of said second conducting type first semiconductor regions. 
     
     
       5. A semiconductor device as claimed in claim 1, wherein a distance between adjacent said open sections is Lg, and a distance between any of said open sections and any of said second conducting type third semiconductor regions is ((Ls+Lg)×M+Ls)   wherein Ls is a width of said open section, Lg is a width of said gate electrode material, and M is an integer multiple.   
     
     
       6. A semiconductor device according to claim 1, wherein the second conducting type third semiconductor regions being positioned in the major surface of the semiconductor substrate such that a depletion region has a constant depth in the semiconductor substrate. 
     
     
       7. A semiconductor device having stable breakdown voltage in a wiring area, comprising: a semiconductor substrate (21 and 22) of a first conducting type and having a major surface;   a plurality of first semiconductor regions of a second conducting type embedded into the major surface of said semiconductor substrate (21, 22), positioned in the major surface adjacent to each other such that a depletion layer in the semiconductor substrate is constant between any of the first semiconductor regions;   a plurality of second semiconductor regions of high density diffused material of the first conducting type embedded within each of said first semiconductor regions;   a plurality of elongated third semiconductor regions of the second conducting type embedded within the major surface of the semiconductor substrate, each of the third semiconductor regions having a longitudinal axis and two ends, each longitudinal axis parallel to any other longitudinal axis, said first semiconductor regions situated adjacent to the two ends;   a gate electrode material (26) formed over the major surface of said semiconductor substrate, the gate electrode material (26) not being in contact with each of said second semiconductor regions (28);   an elongated insulating film (29) positioned on the major surface of the semiconductor substrate forming a plane perpendicular to any of said longitudinal axis of the third semiconductor regions and forming one continuous layer covering a portion of each of the third semiconductor regions;   metal source wiring (211) connected to said second semiconductor regions (28) and to the two ends of each of the third semiconductor regions (24);   metal gate wiring (23) deposited on the elongated insulating film (29) and connected to gate electrode material (26) through open sections in the insulating film such that there is no said third semiconductor regions below the metal gate wiring where the metal gate wiring connects to the gate electrode material; and   wherein a diffusion depth of said third semiconductor regions is substantially equal to the diffusion depth of the first semiconductor regions, the first semiconductor regions and the third semiconductor regions are positioned such that the depletion layer has a constant depth within the semiconductor substrate, and said second semiconductor region (28) is not formed in said third semiconductor region (24).