Non-fully-decoded test address generator

Abstract

An address count which increases up to, or decreases down from, a user-selected value is generated by a non-fully-decoded address generator (10) which is configured of a plurality of interconnected, sequentially-actuated of bit generators (12' 1 -12' k ), each generating a separate one of the bits of the address count. Each of the bit generators is presettable to at least one logic state, with at least one bit generator being presettable to a separate one of two logic states. A control circuit (30' presets the bit generators in accordance to the user-selected initial value so that when the bit generators are sequentially actuated, their collective count runs up to, or down from, the seed value.

I claim: 
     
       1. An address generator for generating bits that form an address count which increases to, or decreases from a user-selected initial seed value, comprising: counter means, including a plurality of bit generators interconnected in daisy chain fashion, each bit generator including a flip-flop and logic circuitry, a first one of the bit generators being responsive to external signals for generating first and second actuating signals to actuate a successive bit generator and for generating a bit in response to said external signals, each successive bit generator generating first and second actuating signals for actuating a successive bit generator and also generating a bit in response to the first and second actuating signals from a preceding bit generator, the bits of the bit generators forming an address count that runs between zero and a user-selected initial seed value, the bit generators each being presettable to only a first prescribed logic state to generate a bit at said first prescribed logic state, except for at least one bit generator being presettable to said first prescribed logic state or to a second prescribed logic state to cause said one bit generator to generate a bit at said first or and said second prescribed logic states, respectively, so that said bit generators, when preset, establish the user-selected initial seed value; and   counter control means for presetting each of the bit generators so that the address count runs between zero and the user-selected initial seed value.   
     
     
       2. The apparatus according to claim 1 wherein the flip-flop in each bit generator comprises: a presettable D-type flip-flop for generating first and second output signals, the flip-flop being presettable to at least said first prescribed logic state to produce an first output signal at one of its, first and second outputs corresponding to said first prescribed logic state, said first output signal of the D-type flip-flop serving as the first actuating signal; and wherein the logic circuit includes:   a NOR gate for logically NORing the first and second actuating signals received from the preceding bit generator to generate the second actuating signal;   an exclusive NOR gate for exclusively NORing the output signal of the NOR gate with the first output signal of the D-type flip-flop to generate a signal applied to the flip-flop; and   logic gate means for logically combining the first and second output signals of the D-type flip-flop with each of a pair of eternally provided UP and DOWN signals, respectively, said UP and DOWN signals are at a first logic level when the address generator is to count up and down, respectively, to generate the count bit wherein said externally provided UP and DOWN signals constitute said external signals.   
     
     
       3. The apparatus according to claim 2 wherein the flip-flop in each bit generator is presettable to either of said first or second prescribed logic states. 
     
     
       4. The apparatus according to claim 1 wherein the counter control means comprises: a first AND gate for logically ANDing a first externally supplied signal of said external signals, indicative of the initial seed value, and a second externally supplied counter increment signal which constitutes another of said external signals;   a first OR gate for ORing the output signal of the first AND gate with an externally supplied reset signal to produce a first preset signal for presetting each bit generator which is presettable to at least said first logic state;   a second AND gate for ANDing the first preset signal produced by said first OR gate with an externally provided DOWN signal, which is asserted when the address generator is to count down, to generate a second preset signal;   an inverter for inverting the DOWN signal and for generating an output; and   a third AND gate for logically ANDing the first preset signal with the output signal of the inverter to yield a third preset signal, the second and third preset signals for presetting each bit generator that is presettable to either the first or second logic state.   
     
     
       5. A method for generating a count which runs between zero and an initial user-selected initial seed value comprising the steps of: providing a plurality of bit generators interconnected in daisy-chain fashion, each bit generator including a flip-flop and associated logic Circuitry for generating first and second actuating signals and also generating a bit in response to the first and second actuating signals from a preceding bit generator, the bits of the bit generators representing an address count that runs between zero and an initial user-selected seed value, with the first bit generator being responsive to external signals, the bit generators each being presettable to only a first prescribed logic state to generate a bit at said first prescribed logic state except for at least one bit generator being presettable to said first prescribed logic state or to a second prescribed logic state to cause said one bit generator to generate a bit at said first or second prescribed logic states, respectively so that said bit generators, when preset, establish the user-selected initial seed value;   presetting the bit generators to preset at least one bit generator to either a first or second logic state and to preset each remaining bit generator to said first prescribed logic state; and   sequentially actuating the bit generators to successively change their bits, with the first bit generator being activated by said external signals, and each successive bit generator activated by each preceding bit generator, so the count formed by the bits, when the bit counters are sequentially actuated, runs between the user-selected initial seed value and zero.