Control circuit for array of light-emitting diodes

Abstract

An array of LEDs is controlled by a control circuit so as to emit light in a write mode and sense light in a read mode. In the read mode, each LED is alternately charged for a first interval, then allowed to discharge by flow of photocurrent for a second interval. At the end of the second interval, just before charging of the LED begins again, the anode voltage of the LED is read by coupling the anode of the LED to an output terminal for a third interval. The third interval of each LED may coincide with the first interval of the preceding LED in tile array, so that each LED is read while the preceding LED is being charged.

What is claimed is: 
     
       1. A method of reading stored charges from an array of light-emitting diodes used for sensing as well as emitting light, comprising the steps of: charging the light-emitting diodes in said array for mutually non-overlapping first intervals of time of equal first lengths;   allowing said light-emitting diodes to discharge by flow of photocurrent for respective second intervals of time of equal second lengths; and   detecting anode voltages of said light-emitting diodes during mutually non-overlapping third intervals of time, said third intervals being contained in respective second intervals and comprising final portions of respective second intervals.   
     
     
       2. The method of claim 1, wherein the steps of charging said light-emitting diodes and allowing said light-emitting diodes to discharge are repeated cyclically. 
     
     
       3. The method of claim 2 wherein, for each light-emitting diode in said array, an interval of time is left between the step of detecting and the step of charging. 
     
     
       4. The method of claim wherein, if a first light-emitting diode is followed by a second light-emitting diode in said array, the third interval in which the anode voltage of said second light-emitting diode is detected coincides with the first interval in which said first light-emitting diode is charged. 
     
     
       5. A control circuit for controlling an array of light-emitting diodes in a write mode in which said light-emitting diodes emit light responsive to data, and a read mode in which charges stored in the light-emitting diodes are read to detect illumination received by said light-emitting diodes, comprising: a first shift register for serially receiving and shifting said data;   a latch coupled to receive said data in parallel from said first shift register, latch said data, and generate corresponding data signals;   an output terminal; and   a switch-and-driver circuit coupled to control said light-emitting diodes responsive to said data signals; wherein   each of said light-emitting diodes has a cathode and an anode, said cathode being grounded in said write mode and biased at positive potential in said read mode, so that an electrical capacitance exists between said anode and said cathode in said read mode; and wherein   said switch-and driver circuit separately comprises, for each light-emitting diode in said array:   a first switching element coupled to supply a driving potential to the anode of said light-emitting diode, said first switching element being switched on to light said light-emitting diode in said write mode, switched off to extinguish said light-emitting diode in said write mode, and switched off in said read mode;   a second switching element coupled to supply a ground potential to the anode of said light-emitting diode, said second switching element being switched off to light said light-emitting diode in said write mode, switched on to extinguish said light-emitting diode in said write mode, switched on to charge the capacitance of said light-emitting diode in said read mode, and switched off in said read mode when not charging the capacitance of said light-emitting diode; and   a third switching element for coupling the anode of said light-emitting diode to said output terminal, said third switching element being switched off in said write mode, switched off when said light-emitting diode is being charged by said second switching element in said read mode, and switched on to read an anode voltage of said light-emitting diode just before said light-emitting diode is charged in said read mode.   
     
     
       6. The control circuit of claim 5, wherein said first switching element is a bipolar transistor. 
     
     
       7. The control circuit of claim 5, wherein said first switching element is a field-effect transistor. 
     
     
       8. The control circuit of claim 5, wherein said second switching element is a field-effect transistor. 
     
     
       9. The control circuit of claim 5, wherein said third switching element is a field effect transistor. 
     
     
       10. The control circuit of claim 5, wherein said third switching element is an analog switch comprising a pair of field-effect transistors of opposite channel types coupled in parallel between the anode of said light-emitting diode and said output terminal. 
     
     
       11. The control circuit of claim 5, also comprising a buffer amplifier for amplifying anode voltages of said light-emitting diodes prior to output of said anode voltages at said output terminal in said read mode. 
     
     
       12. The control circuit of claim 11, wherein: said first shift register stores at least a first bit and a last bit, data being shifted from said first bit toward said last bit; and   said control circuit also comprises a chip selector for switching said buffer amplifier on responsive to said first bit, and off responsive to said last bit.   
     
     
       13. The control circuit of claim 12, wherein: said array contains N light-emitting diodes, N being a positive integer; and   said first shift register stores N+1 bits of data.   
     
     
       14. The control circuit of claim 5, also comprising: a second shift register for serially receiving and shifting a scan input, and generating a plurality of scan signals, each third switching element in said switch-and-driver circuit being controlled by a respective one of said scan signals.   
     
     
       15. The control circuit of claim 14, wherein said switch-and-driver circuit 22 receives a read/write signal for selecting said read mode and said write mode, and separately comprises, for each light-emitting diode in said array: a first logic gate for controlling said first switching element responsive to said read/write signal and one of said data signals; and   a second logic gate for controlling said second switching element responsive to said read/write signal and said one of said data signals.   
     
     
       16. The control circuit of claim 15, wherein said first logic gate is all AND gate and said second logic gate is an exclusive OR gate. 
     
     
       17. The control circuit of claim 15, comprising a plurality of third logic gates for receiving a strobe signal that controls durations during which said light-emitting diodes can emit light in said write mode, and gating outputs of said latch, responsive to said strobe signal, prior to input to said switch-and-driver circuit. 
     
     
       18. The control circuit of claim 5, wherein said second switching element comprises a pair of transistors coupled in parallel between the anode of said light-emitting diode and said ground potential, said pair including a first transistor for extinguishing said light-emitting diode in said write mode, and a second transistor for charging the capacitance of said light-emitting diode in said read mode. 
     
     
       19. The control circuit of claim 18, wherein: said array contains N light-emitting diodes, N being a positive integer;   said first shift register stores N+1 bits of data; and   said switch-and driver circuit has:   a first N stages, each with a first switching element as described in claim 5, a second switching element as described in claim 18, and a third switching element as described in claim 5; and   a last stage for controlling the second transistor of said second switching element in an Nth state among said first N stages.   
     
     
       20. The control circuit of claim 19, wherein said switch-and-driver circuit 62 receives a read/write signal for selecting said read mode and said write mode, and a strobe signal for controlling durations during which said light-emitting diodes can emit light in said write mode, and wherein each individual stage among said first N stages separately comprises: a fourth logic gate for controlling said first switching element in said individual stage responsive to said read/write signal, said strobe signal, and one of said data signals;   a fifth logic gate for controlling said first transistor in said second switching element in said individual stage, responsive to said read/write signal and an output of said fourth logic gate; and   a sixth logic gate for controlling said third switching element in said individual stage and said second transistor in said second switching element in a preceding stage among said First N stages, responsive to said read/write signal and said one of said data signals.   
     
     
       21. The control circuit of claim 20, wherein said fourth logic gate is a NAND gate. 
     
     
       22. The control circuit of claim 20, wherein said fifth logic gate is an AND gate. 
     
     
       23. The control circuit of claim 20, wherein said sixth logic gate is a NAND gate. 
     
     
       24. The control circuit of claim 20, further comprising an inhibiting circuit for producing inhibit pulses, which are supplied to each said sixth logic gate to delay switching-on of said third switching elements. 
     
     
       25. The control circuit of claim 24, wherein said inhibiting circuit receives a clock signal and comprises: a NAND gate having a first input terminal and a second input terminal, said clock signal being received at said first input terminal;   an inverter coupled to invert said clock signal, and supply an inverted clock signal to the second input terminal of said NAND gate; and   a capacitor coupled to the second input terminal of said NAND gate.   
     
     
       26. The control circuit of claim 20, also comprising, for each said sixth logic gate, a delay line for delaying the data signal input to said sixth logic gate, said sixth logic gate receiving both delayed and undelayed data signals.