Methods for adjusting the coupling capacitor of a multi-stage weighted capacitor A/D converter

Abstract

A circuit for adjusting capacitors in a capacitor analog to digital converter has a main capacitor array including more than one capacitor array portion 20 and 22, and at least one first coupling capacitor C c . A first plate of each first coupling capacitor C c is coupled to one capacitor array portion 22 and a second plate of each first coupling capacitor C c is coupled to a next more significant capacitor array portion 20 such that each capacitor array portion is coupled to the next more significant capacitor array portion by one of the first coupling capacitors C c . The circuit has at least one second coupling capacitor C c3 with a first plate of each second coupling capacitor C c3 coupled to the first plate of a corresponding one of the first coupling capacitors C c . The circuit also has at least one array of calibration capacitors 60-84 with first plates of each array of calibration capacitors 60-84 coupled to a second plate of a corresponding one of the second coupling capacitors C c3 and second plates of each array of calibration capacitors 60-84 coupled to corresponding switches 100-124. Switch control signals S c4 , S c3 , S c2 , S c1 , and S c0 , and S 4 , S 3 , S 2 , S 1 , and S 0 control the switches such that each switch connects the corresponding calibration capacitor to either a first node V ref+ or a second node V ref- . Each switch control signal consists of two switch control bits which are combined by a logic function.

What is claimed is: 
     
       1. A circuit for adjusting capacitors in a capacitor analog to digital converter comprising: a main capacitor array including: more than one capacitor array portion;   at least one first coupling capacitor, a first plate of each first coupling capacitor coupled to one capacitor array portion and a second plate of each first coupling capacitor coupled to a next more significant capacitor array portion such that each capacitor array portion is coupled to the next more significant capacitor array portion by one of the at least one first coupling capacitor;     at least one second coupling capacitor, a first plate of each second coupling capacitor coupled to the first plate of a corresponding one of the at least one first coupling capacitor;   at least one array of calibration capacitors, first plates of each array of calibration capacitors coupled to a second plate of a corresponding one of the at least one second coupling capacitor and second plates of each array of calibration capacitors coupled to corresponding switches;   switch control signals which control the switches such that each switch connects the corresponding calibration capacitor to either a first node or a second node, each switch control signal consists of a horizontal switch control bit and a vertical switch control bit;   each array of calibration capacitors is arranged in rows and columns with each horizontal switch control bit associated with a corresponding one of the rows and each vertical switch control bit associated with a corresponding one of the columns.   
     
     
       2. The circuit of claim 1 wherein the at least one array of calibration capacitors are binary weighted arrays. 
     
     
       3. The circuit of claim 1 wherein each calibration capacitor consists of one or more unit capacitors. 
     
     
       4. The circuit of claim 1 wherein the vertical switch control bits also serve as the switch control bits for the capacitor array portion that is coupled to the first plate of the corresponding one of the at least one first coupling capacitor. 
     
     
       5. The circuit of claim 1 wherein all the rows in each array of calibration capacitors contain the same number of calibration capacitors. 
     
     
       6. The circuit of claim 5 wherein the number of calibration capacitors in each row is equal to the number of bits in the capacitor array portion that is coupled to the first plate of the corresponding one of the at least one first coupling capacitor. 
     
     
       7. The circuit of claim 1 wherein all the rows in each array of calibration capacitors do not contain the same number of calibration capacitors. 
     
     
       8. The circuit of claim 7 wherein each row in the array of calibration capacitors contains one more calibration capacitor than the previous row. 
     
     
       9. The circuit of claim 8 wherein the number of calibration capacitors in the row with the most calibration capacitors is equal to the number of bits in the capacitor array portion that is coupled to the first plate of the corresponding one of the at least one first coupling capacitor. 
     
     
       10. The circuit of claim 1 wherein the first node is coupled to a first reference voltage and the second node is coupled to a second reference voltage. 
     
     
       11. A circuit for adjusting capacitors in a capacitor analog to digital converter comprising: a main capacitor array including: more than one capacitor array portion;   at least one coupling capacitor, a first plate of each coupling capacitor coupled to one capacitor array portion and a second plate of each coupling capacitor coupled to a next more significant capacitor array portion such that each capacitor array portion is coupled to the next more significant capacitor array portion by one of the at least one coupling capacitor;     at least one first calibration capacitor, a first plate of each first calibration capacitor coupled to the first plate of a corresponding one of the at least one coupling capacitor;   at least one array of second calibration capacitors, first plates of each array of second calibration capacitors coupled to a second plate of a corresponding one of the at least one first calibration capacitor and second plates of each array of second calibration capacitors coupled to corresponding switches;   switch control signals which control the switches such that each switch connects the corresponding second calibration capacitor to either a second plate of the corresponding one of the at least one coupling capacitor or a reference voltage.   
     
     
       12. The circuit of claim 11 wherein the array of second calibration capacitors comprises a binary weighted array. 
     
     
       13. The circuit of claim 11 wherein each of the second calibration capacitors consists of one or more unit capacitors. 
     
     
       14. The circuit of claim 11 wherein the reference voltage is ground voltage. 
     
     
       15. A method for adjusting capacitors in a capacitor analog to digital converter having a main capacitor array including more than one capacitor array portion and at least one first coupling capacitor, comprising: coupling a first plate of each first coupling capacitor to one capacitor array portion and coupling a second plate of each first coupling capacitor to a next more significant capacitor array portion such that each capacitor array portion is coupled to the next more significant capacitor array portion by one of the at least one first coupling capacitor;   coupling a first plate of at least one second coupling capacitor to the first plate of a corresponding one of the at least one first coupling capacitor;   coupling first plates of at least one array of calibration capacitors to a second plate of a corresponding one of the at least one second coupling capacitor and coupling second plates of each array of calibration capacitors to corresponding switches;   switching the second plate of each calibration capacitor to either a first reference voltage or a second reference voltage using switch control signals to control the corresponding switch, each switch control signal consisting of a horizontal switch control bit and a vertical switch control bit;   arranging each array of calibration capacitors in rows and columns with each horizontal switch control bit associated with a corresponding one of the rows and each vertical switch control bit associated with a corresponding one of the columns.   
     
     
       16. The method of claim 15 wherein the at least one array of calibration capacitors are binary weighted arrays. 
     
     
       17. The method of claim 15 wherein the second reference voltage is ground voltage.