Decimation circuit and method for filtering quantized signals while providing phase angle correction with a substantially linear phase response

Abstract

A decimation circuit for filtering a stream of quantized electrical signals while providing phase angle correction and a substantially linear phase response over a predetermined passband range F B is provided. The stream of quantized electrical signals arrives at a predetermined rate F M from an oversampling delta-sigma modulator. The decimation circuit includes a decimation filter for filtering the stream of quantized electrical signals to provide a filtered output signal at an output ram F' S defined by F' S =F M /R wherein R is a positive integer. A phase corrector is coupled to the decimation filter to receive the filtered output signal and to correct the phase angle of the received filtered signal so as to provide an equalized phase angle at least over the predetermined range F B . The value for R is selected such that output rate F' S is sufficiently situated above bandpass range F B such that the phase corrector provides a desired substantially linear phase response over the passband range F B .

What is claimed is: 
     
       1. A circuit for filtering a stream of quantized electrical signals from an analog-to-digital converter while providing a phase angle correction and a substantially linear phase response over a predetermined passband range F B , said stream of quantized electrical signals having a predetermined rate F M , said circuit comprising: a decimation filter for filtering said stream of quantized electrical signals and adapted to provide a filtered output signal at an output rate F' S  defined by F' S  =F M  /R wherein R is a positive integer; and   a phase corrector coupled to said decimation filter to to receive said filtered output signal to predeterminedly correct the phase angle of said filtered output signal at least over said predetermined passband range F B , said phase corrector comprising an infinite impulse response (IIR) digital filter having a z domain response defined by: ##EQU1## wherein α is a number such that |α|<1.   
     
     
       2. The circuit of claim 1 wherein said IIR digital filter comprises: a first digital summer having first and second inputs, said first digital summer for receiving at the first input thereof the filtered output signal from said decimation filter and for receiving at the second input thereof a feedback signal, said first digital summer adapted to produce a respective combined output signal;   a digital multiplier coupled to said first digital multiplier to receive the combined output signal produced therein and adapted to multiply said received combined output signal by a multiplying factor substantially corresponding to said α number;   a digital subtractor for receiving the filtered signal from said decimation filter as a minuend input signal and for receiving the output signal from said multiplier as a subtrahend input signal, said digital subtractor adapted to produce a difference output signal;   a delay unit coupled to said digital subtractor to receive the difference output signal produced therein and adapted to produce a delayed difference signal constituting the feedback signal received by said first digital summer; and   a second digital summer having first and second inputs, said second digital summer for receiving at the first input thereof the delayed difference signal and for receiving at the second input thereof the output signal from said multiplier, said second digital summer adapted to produce a combined output signal constituting the output signal of said IIR filter.   
     
     
       3. The circuit of claim 2 wherein said digital multiplier comprises a multibit floating point multiplier. 
     
     
       4. The circuit of claim 2 wherein said digital subtractor comprises a multibit floating point subtractor. 
     
     
       5. The circuit of claim 2 wherein said first and second summers comprise respective multibit floating point summers. 
     
     
       6. The circuit of claim 1 wherein R is selected such that output rate F' S  is sufficiently situated above passband range F B  such that said phase corrector provides a desired substantially linear phase response over said predetermined passband range F B . 
     
     
       7. The circuit of claim 1 wherein said analog-to-digital converter is an oversampled sigma-delta modulator. 
     
     
       8. A circuit for filtering a stream of quantized electrical signals while providing a phase-angle correction and a substantially linear phase response over a predetermined passband range F B , said stream of quantized electrical signals having a predetermined rate FM, said circuit comprising: a single monolithic electronic integrated circuit chip incorporating a delta-sigma modulator for providing said stream of quantized electrical signals;   said chip further including:   a decimation filter for filtering said stream of quantized electrical signals and adapted to provide a filtered output signal at an output rate F' S  defined by F' S  =F M  /R wherein R is a positive integer; and   a phase corrector coupled to said decimation filter to receive said filtered output signal to predeterminedly correct the phase angle of said filtered output signal at least over said predetermined passband range F B , said phase corrector comprising an infinite impulse response (IIR) digital filter having a Z domain response defined by: ##EQU2## wherein α is a number such that |α↑<1; R being selected such that output rate F' S  is sufficiently situated above passband range F B  such that said phase corrector provides a desired substantially linear phase response over said predetermined passband range F B .   
     
     
       9. The circuit of claim 8 wherein said IIR digital filter comprises: a first digital summer having first and second inputs, said first digital summer for receiving at the first input thereof the filtered output signal from said decimation filter and for receiving at the second input thereof a feedback signal, said first digital summer adapted to produce a respective combined output signal;   a digital multiplier coupled to said first digital multiplier to receive the combined output signal produced therein and adapted to multiply said received combined output signal by a multiplying factor substantially corresponding to said a number;   a digital subtractor for receiving the filtered signal from said decimation filter as a minuend input signal and for receiving the output signal from said multiplier as a subtrahend input signal, said digital subtractor adapted to produce a difference output signal;   a delay unit coupled to said digital subtractor to receive the difference output signal produced therein and adapted to produce a delayed difference signal constituting the feedback signal received by said first digital summer; and   a second digital summer having first and second inputs, said second digital summer for receiving at the first input thereof the delayed difference signal and for receiving at the second input thereof the output signal from said multiplier, said second digital summer adapted to produce a combined output signal constituting the output signal of said IIR filter.   
     
     
       10. The circuit of claim 9 wherein said digital multiplier comprises a multibit floating point multiplier. 
     
     
       11. The circuit of claim 9 wherein said digital subtractor comprises a multibit floating point subtractor. 
     
     
       12. The circuit of claim 9 wherein said first and second summers comprise respective multibit floating point summers. 
     
     
       13. A method for filtering a stream of quantized electrical signals while providing a phase angle correction and a substantially linear response over a predetermined passband range F B , said stream of quantized electrical signals having a predetermined rate F M , said method comprising: decimation filtering said stream of quantized electrical signals to provide a filtered output signal having an output rate F' S  defined by F' S  =F M  /R wherein R is a positive integer;   selecting R such that output rate F' S  is sufficiently situated above passband range F B  to provide a desired substantially linear phase response over said predetermined passband range F B  ; and   correcting a phase angle of said filtered output signal at least over said predetermined passband range F B .