Word line selection circuit for selecting memory cells

Abstract

A selection circuit of the present invention comprises a plurality of word lines each of which is coupled to a plurality of memory cells, the word lines including first and second groups of word lines, a first decode line group having a plurality of first decode lines each of which is coupled to the first group of the word lines, a second decode line group having a plurality of second decode lines each of which is coupled to the second group of the word lines, a plurality of address input terminals applied to an address signal, a first input terminal applied to a first signal, a second input terminal applied to a second signal, a first selecting switch coupled to the first and second decode line groups and the address input terminals for selecting one of the decode lines in response to the address signal, a second selecting switch coupled to the first decode line group and the first input terminal for selecting the first decode lines in response to the first signal and a third selecting switch coupled to the second decode line group and the second input terminal for selecting the second decode lines in response to the second signal.

What is claimed is: 
     
       1. A word line selecting circuit comprising: a plurality of word lines each of which is coupled to a plurality of memory cells;   a plurality of decode lines each of which is coupled to one of said word lines;   a plurality of address input terminals applied to an address signal;   a first input terminal applied to a first signal;   a first selecting switch coupled to said decode lines and said address input terminals for activating one of said decode lines in response to the address signal;   a second selecting switch coupled to one of the decode lines and said first input terminal for activating the decode line in response to the first signal; and   a plurality of third selecting switches coupled to each of the decode lines for serially activating the other decode lines in response to the activation of the preceding decode line.   
     
     
       2. A word line selecting circuit according to claim 1, wherein said first selecting switch comprises a plurality of series coupled MOS transistors each of which is coupled between one of said decode lines and a reference potential terminal, for electrically connecting therebetween in response to the address signal applied to the gates of series coupled MOS transistors. 
     
     
       3. A word line selecting circuit according to claim 1, wherein each of said third selecting switches comprises a plurality of MOS transistors each of which is coupled between the respective decode lines, for activating the respective decode line in response to the activation of the preceding decode line. 
     
     
       4. A word line selecting circuit according to claim 1, wherein said second selecting switch comprises a MOS transistor coupled between one of the decode lines and a reference potential terminal, for electrically connecting therebetween in response to the first signal applied to the gate of the MOS transistor. 
     
     
       5. A word line selecting circuit comprising: a reset terminal to which a reset signal is applied;   a plurality of word lines each of which is coupled to a plurality of memory cells;   a plurality of decode lines each of which is coupled to one of said word lines;   a first reset selecting switch coupled to each of said decode lines and said reset terminal for activating the decode lines in response to said reset signal; and   a plurality of second reset selecting switches each of which is coupled to a respective one of said decode lines and each of which activates respective decode lines in response to each preceding said second reset selecting switch.