Method for fabricating a self-aligned multi-level interconnect

Abstract

A self-aligned multi-level interconnect structure and a method for fabricating the same are disclosed. The multi-level interconnect structure is fabricated by the steps of: (1) forming a first plurality of spaced-apart insulative layers [231-233], where the first plurality includes a top insulative layer [233]; (2) forming a second plurality of spaced-apart conductors [221,222] and positioning them interdigitally between the insulative layers; (3) defining a first hole [233h] extending through the top insulative layer [233]; (4) using the first hole [233h] to define a succession of self-aligned subsequent holes [222h,232h,22ih,231h] through the underlying conductors and insulative layers, each successive hole being continuous with and self-aligned to one above it; and (5) defining a through-conductor [223] extending through the succession of self-aligned holes. The self-aligned multi-level interconnect structure is employed in a multi-layer SRAM cell.

What is claimed is: 
     
       1. A fabricating method for fabricating in an integrated circuit having a substrate, an interconnect network that interconnects plural devices of the integrated circuit, said method comprising the steps of: forming a first plurality of spaced-apart insulative layers on said substrate, said first plurality including a top insulative layer;   forming a second plurality of spaced-apart conductors and positioning them interdigitally relative to said insulative layers, said conductors being below the top insulative layer;   defining a first hole extending through the top insulative layer;   using the first hole for defining a succession of self-aligned subsequent holes through at least two of the underlying plural conductors and at least one underlying insulative layer, each successive hole being continuous with and self-aligned to one above it;   defining a through-conductor extending through said first hole and said succession of self-aligned subsequent holes and electrically coupling to at least one of said at least two spaced-apart conductors; and   performing a contact-area enhancing step after said step of using the first hole to define a succession of self-aligned subsequent holes but before said step of defining a through-conductor;   wherein the contact-area enhancing step includes widening one or more of the first hole and insulator-piercing ones of the succession of self-aligned subsequent holes so as to increase an exposed surface area of a corresponding one or more of said second plurality of spaced-apart conductors, the exposed surface area being that exposed by said first hole and succession of self-aligned subsequent holes.   
     
     
       2. A fabricating method according to claim 1 further comprising the steps of: depositing a resist layer on the top insulative layer prior to the step of defining said first hole through the top insulative layer;   defining a reference hole extending through the resist layer; and   using the reference hole to define said first hole and thereafter said succession of self-aligned subsequent holes through the underlying conductors and insulative layers.   
     
     
       3. A fabricating method according to claim 2 wherein the substrate has a contract region defined thereon, and said step of defining a reference hole includes: aligning said reference hole over the contact region; and   thereafter defining said succession of self-aligned subsequent holes through the underlying conductors and insulative layers so as to expose the contact region.   
     
     
       4. A fabricating method according to claim 3 wherein said substrate includes semiconductor material. 
     
     
       5. A fabricating method according to claim 4 wherein said substrate includes a plurality of regions of different conductivities, said plurality of regions defining the plural devices of the integrated circuit, and wherein the contact region defines one such region. 
     
     
       6. A fabricating method according to claim 5 wherein said second plurality of spaced-apart conductors are composed of conductive semiconductors each selected from the group consisting of a P conductivity type semiconductor and a N conductivity type semiconductor. 
     
     
       7. A fabricating method according to claim 6 wherein said through-conductor is composed of a conductive semiconductor selected from the group consisting of a P conductivity type semiconductor and a N conductivity type semiconductor. 
     
     
       8. A fabric method according to claim 7 wherein said through-conductor is composed of polycrystalline silicon. 
     
     
       9. A fabricating method according to claim 8 wherein one or more of said second plurality of spaced-apart conductors is composed of polycrystalline silicon. 
     
     
       10. A fabricating method according to claim 2 wherein the first plurality of insulative layers and interdigitated second plurality of conductors are respectively composed of etch-differentiated materials such that one can be differentially etched without substantial etching into a directly underlying other;   wherein said step for defining a succession of self-aligned subsequent holes includes: using a layer-specific differential etchant for respectively and differentially etching through each of the first plurality of insulative layers below the top insulative layer and through each of the interdigitated second plurality of conductors to thereby respectively define the self-aligned subsequent holes; and     wherein said step of depositing a resist layer includes: selecting the thickness and material of the resist layer such that the resist layer can survive the subsequent, combined series of hole-defining steps that define the first hole and the succession of self-aligned subsequent holes.     
     
     
       11. A fabricating method according to claim 3 wherein the step of defining the through-conductor includes extending it to contact said contact region. 
     
     
       12. A fabricating method according to claim 11 wherein the through-conductor and contact region are each composed of doped semiconductor material and are each doped to have a same conductivity type. 
     
     
       13. A fabricating method according to claim 11 wherein the through-conductor is composed of N or P doped polysilicon. 
     
     
       14. A fabricating method according to claim 7 wherein the conductivity type of said through-conductor is the same as that of at least two of said spaced-apart conductors. 
     
     
       15. A fabricating method according to claim 14 wherein the through-conductor provides an ohmic connection path between the at least two of said spaced-apart conductors of same conductivity type. 
     
     
       16. A fabricating method according to claim 14 wherein one of said spaced-apart conductors with a same conductivity type as said through-conductor is doped substantially more lightly than the through-conductor to thereby define an integrated resistive element within the fabricated interconnect network. 
     
     
       17. A fabricating method according to claim 14 wherein one of said spaced-apart conductors with a same conductivity type as said through-conductor is doped substantially more lightly than a second of said spaced-apart conductors to thereby define an integrated resistive element within the fabricated interconnect network. 
     
     
       18. A fabricating method according to claim 7 wherein the conductivity type of said through-conductor is set different from that of at least one of said spaced-apart conductors to thereby define an integrated PN junction within the fabricated interconnect network. 
     
     
       19. A fabricating method according to claim 1 wherein said substrate has a contact region of one of said plural devices defined on an upper surface of the substrate;   wherein the steps of forming said interdigitated insulative and conductive layers place the lowermost of the insulative layers on the substrate, overlying the contact region;   wherein said step of defining the first hole includes aligning said first hole over the contact region; and   wherein said steps of thereafter defining said succession of self-aligned subsequent holes through the underlying conductors and insulative layers exposes the contact region.   
     
     
       20. A fabricating method according to claim 1 wherein the second plurality of spaced-apart conductors includes three or more conductors and said step for defining the succession of self-aligned subsequent holes cuts through at least three of the underlying plural conductors. 
     
     
       21. A fabricating method according to claim 1 wherein the conductors of said second plurality of spaced-apart conductors are composed of a conductive semiconductor material. 
     
     
       22. A fabricating method according to claim 21 wherein the conductors of said second plurality of spaced-apart conductors are composed of conductive polycrystalline silicon. 
     
     
       23. A fabricating method according to claim 1 wherein the first plurality of insulative layers and interdigitated second plurality of conductors are respectively composed of etch-differentiated materials such that one can be differentially etched without substantial etching into a directly underlying other; and   wherein said step for defining a succession of self-aligned subsequent holes includes: using a layer-specific differential etchant for respectively and differentially etching through each of the first plurality of insulative layers below the top insulative layer and through each of the interdigitated second plurality of conductors to thereby respectively define the self-aligned subsequent holes.     
     
     
       24. A fabricating method according to claim 23 wherein said first plurality of insulative layers each consists essentially of one or more silicon oxide compounds and the differential etchant used for differentially etching through each of the first plurality of insulative layers below the top insulative layer is selected from the oxide-specific etchant group consisting of: CF 4 , C 2  F 6 , CHF 3  and SF 6 . 
     
     
       25. A fabricating method according to claim 24 wherein said second plurality of conductors each consists essentially of silicon and the differential etchant used for differentially etching through each of the second plurality of conductors is selected from the silicon-specific etchant group consisting of: Cl 2  and CFCl 3 . 
     
     
       26. A fabricating method according to claim 23 wherein the etch-differentiated materials of the first plurality of insulative layers are selected from the group consisting of silicon oxides, silicon nitrides, and silicon oxy-nitrides (Si x  O y  N z ); and   wherein the corresponding etch-differentiated materials of the second plurality of conductors are selected from the group consisting of: doped silicon, aluminum, copper, tungsten, titanium and cobalt.   
     
     
       27. A fabricating method according to claim 23 wherein the etch-differentiated nature of the first plurality of insulative layers and interdigitated second plurality of conductors is used to stop the depth of the succession of self-aligned subsequent holes at any desired layer above the substrate. 
     
     
       28. A fabricating method according to claim 23 wherein said step for differentially defining the succession of self-aligned subsequent holes is performed by anisotropic plasma etching. 
     
     
       29. A fabricating method according to claim 1 wherein the step of defining the through-conductor includes electrically coupling the through-conductor to at least two of said spaced-apart conductors; and   wherein one of the coupled-to spaced-apart conductors defines the gate electrode of a field effect transistor.   
     
     
       30. A fabricating method according to claim 29 wherein another of the coupled-to spaced-apart conductors defines the source, channel and drain of a thin-film field effect transistor. 
     
     
       31. A fabricating method for fabricating an interconnect structure that interconnects plural devices, said method comprising the steps of: forming a first plurality of spaced-apart insulative layers, said first plurality including a top insulative layer;   forming a second plurality of spaced-apart conductors and positioning them interdigitally relative to said insulative layers;   defining a first hole extending through the top insulative layer;   using the first hole for defining a succession of self-aligned subsequent holes through the underlying conductors and insulative layers, each successive hole being continuous with and self-aligned to one above it; and   defining a through-conductor extending through said succession of self-aligned holes and contacting at least two of said spaced-apart conductors;   wherein said steps of defining the first hole and succession of self-aligned subsequent holes respectively include use of an anisotropic etch process that is selective to the material through which the respective one of the first hole and succession of self-aligned subsequent holes is being defined; and   before said step of defining the through-conductor, selectively and isotropically removing some of the insulative material exposed by said succession of self-aligned holes, to thereby increase the surface area of at least one of the conductors exposed by said succession of self-aligned holes and subsequently contacted by the through-conductor.   
     
     
       32. A fabricating method according to claim 31 wherein said step for increasing the surface area of at least one of the conductors increases exposure of one or both of top and bottom surface portions of the at least one conductor. 
     
     
       33. An interconnect fabricating method comprising the steps of: forming a first plurality of spaced-apart insulative layers, said first plurality including a top insulative layer;   forming a second plurality of spaced-apart conductors and positioning them interdigitally relative to said insulative layers;   defining a first hole extending through the top insulative layer;   using the first hole for defining a succession of self-aligned subsequent holes through the underlying conductors and insulative layers, each successive hole being continuous with and self-aligned to one above it;   increasing the effective contactable surface area of at least one of the conductors exposed by said succession of self-aligned holes for thereby increasing effective contact area between the at least one conductor and a subsequently-formed through-conductor; and   defining said through-conductor extending through said succession of self-aligned holes and contacting the at least one conductor whose effective contact surface area has been increased;   wherein the step of increasing the effective contact surface area of the at least one conductor includes one or more of the following substeps; (a) selectively removing some of the insulative material exposed by said succession of self-aligned holes, to thereby increase the surface area of the at least one conductor exposed by said succession of self-aligned holes;   (b) selectively removing spaced apart spots on the surface area of the at least one conductor exposed by said succession of self-aligned holes to thereby leave pits in said surface area of the at least one conductor; and   (c) selectively growing additional conductive material from the surface area of the at least one conductor exposed by said succession of self-aligned holes to thereby create bumps in said surface area of the at least one conductor.     
     
     
       34. A fabricating method according to claim 33 wherein said step for increasing the surface area of the at least one conductor increases exposure of one or both of top and bottom surface portions of the at least one conductor. 
     
     
       35. A fabricating method for fabricating in an integrated circuit having a substrate, an interconnect network that interconnects plural devices of the integrated circuit, said method comprising the steps of: forming a first plurality of spaced-apart insulative layers on said substrate, said first plurality including a top insulative layer;   forming a second plurality of spaced-apart conductors and positioning them interdigitally relative to said insulative layers, said conductors being below the top insulative layer;   defining a first hole extending through the top insulative layer;   using the first hole for defining a succession of self-aligned subsequent holes through at least two of the underlying plural conductors and at least one underlying insulative layer, each successive hole being continuous with and self-aligned to one above it;   defining a through-conductor extending through said first hole and said succession of self-aligned subsequent holes and electrically coupling to at least one of said at least two spaced-apart conductors;   depositing a resist layer on the top insulative layer prior to the step of defining said first hole through the top insulative layer;   defining a reference hole extending through the resist layer;   using the reference hole to define said first hole and thereafter said succession of self-aligned subsequent holes through the underlying conductors and insulative layers;   wherein the substrate has a contact region defined thereon, and said step of defining a reference hole includes: aligning said reference hole over the contact region; and   thereafter defining said succession of self-aligned subsequent holes through the underlying conductors and insulative layers so as to expose the contact region;     wherein said substrate includes semiconductor material having a plurality of regions of different conductivities, said plurality of regions defining the plural devices of the integrated circuit, and wherein the contact region defines one such region;   wherein said second plurality of spaced-apart conductors are composed of conductive semiconductors each having a conductivity selected from the group consisting of P and N;   wherein said through-conductor is composed of a conductive semiconductor having a conductivity selected from the group consisting of P and N;   wherein the conductivity type of said through-conductor is the same as that of at least two of said spaced-apart conductors; and   wherein one of said spaced-apart conductors with a same conductivity type as said through-conductor is doped substantially more lightly than the through-conductor to thereby define an integrated resistive element within the fabricated interconnect network.   
     
     
       36. A fabricating method for fabricating in an integrated circuit having a substrate, an interconnect network that interconnects plural devices of the integrated circuit, said method comprising the steps of: forming a first plurality of spaced-apart insulative layers on said substrate, said first plurality including a top insulative layer;   forming a second plurality of spaced-apart conductors and positioning them interdigitally relative to said insulative layers, said conductors being below the top insulative layer;   defining a first hole extending through the top insulative layer;   using the first hole for defining a succession of self-aligned subsequent holes through at least two of the underlying plural conductors and at least one underlying insulative layer, each successive hole being continuous with and self-aligned to one above it;   defining a through-conductor extending through said first hole and said succession of self-aligned subsequent holes and electrically coupling to at least one of said at least two spaced-apart conductors;   depositing a resist layer on the top insulative layer prior to the step of defining said first hole through the top insulative layer;   defining a reference hole extending through the resist layer;   using the reference hole to define said first hole and thereafter said succession of self-aligned subsequent holes through the underlying conductors and insulative layers;   wherein the substrate has a contact region defined thereon, and said step of defining a reference hole includes: aligning said reference hole over the contact region; and   thereafter defining said succession of self-aligned subsequent holes through the underlying conductors and insulative layers so as to expose the contact region;     wherein said substrate includes semiconductor material having a plurality of regions of different conductivities, said plurality of regions defining the plural devices of the integrated circuit, and wherein the contact region defines one such region;   wherein said second plurality of spaced-apart conductors are composed of conductive semiconductors each having a conductivity selected from the group consisting of P and N;   wherein said through-conductor is composed of a conductive semiconductor having a conductivity selected from the group consisting of P and N; and   wherein the conductivity type of said through-conductor is set different from that of at least one of said spaced-apart conductors to thereby define an integrated PN junction within the fabricated interconnect network.   
     
     
       37. A fabricating method for fabricating in an integrated circuit having a substrate, an interconnect network that interconnects plural devices of the integrated circuit, said method comprising the steps of: forming a first plurality of spaced-apart insulative layers on said substrate, said first plurality including a top insulative layer;   forming a second plurality of spaced-apart conductors and positioning them interdigitally relative to said insulative layers, said conductors being below the top insulative layer;   defining a first hole extending through the top insulative layer;   using the first hole for defining a succession of self-aligned subsequent holes through at least two of the underlying plural conductors and at least one underlying insulative layer, each successive hole being continuous with and self-aligned to one above it; and   defining a through-conductor extending through said first hole and said succession of self-aligned subsequent holes and electrically coupling to at least one of said at least two spaced-apart conductors;   wherein the step of defining the through-conductor includes electrically coupling the through-conductor to at least two of said spaced-apart conductors; and   wherein one of the coupled-to spaced-apart conductors defines the gate electrode of a field effect transistor.   
     
     
       38. A fabricating method according to claim 37 wherein another of the coupled-to spaced-apart conductors defines the source, channel and drain of a thin-film field effect transistor. 
     
     
       39. An interconnect fabricating method comprising the steps of: forming a first plurality of spaced-apart insulative layers, said first plurality including a top insulative layer;   forming a second plurality of spaced-apart conductors and positioning them interdigitally relative to said insulative layers;   defining a first hole extending through the top insulative layer;   using the first hole for defining a succession of self-aligned subsequent holes through the underlying conductors and insulative layers, each successive hole being continuous with and self-aligned to one above it;   increasing the effective contactable surface area of at least one of the conductors exposed by said succession of self-aligned holes for thereby increasing effective contact area between the at least one conductor and a subsequently-formed through-conductor; and   defining said through-conductor extending through said succession of self-aligned holes and contacting the at least one conductor whose effective contact surface area has been increased;   wherein said step for increasing the surface area of the at least one conductor increases exposure of one or both of top and bottom surface portions of the at least one conductor.