Self-tuning receiver/decoder for frequency shift keying RF data transmission

Abstract

A self-tuning receiver/decoder for reception of FSK data transmission. An RF stage with resonant circuit (10) is tuned to a first of four possible transmitted frequencies for reception of such frequencies according to interrogation at such frequencies in sequence. Threshold (18) and counter circuits (12, 16) detect each frequency shift change of transmitted frequency and accordingly retune the resonant circuit to a subsequent unknown frequency by counting through a predetermined sequence for possible reception of each of such frequencies. Provision (24) is made for latching frequency shift data bit signals accordingly as output in a format identical to the frequency shift-keying RF format received. The receiver/decoder is especially useful for miniaturized transponder operation in which it alternates between receiving and transmitting modes, and is powered by capacitively stored charge in response to continuous transmission of the first frequency over a period.

What is claimed is: 
     
       1. A self-tuning receiver/decoder for reception of frequency shift-keying RF data transmission, including a radio frequency stage comprising resonant circuit means for being tuned to a first frequency of a plurality of more than two other frequencies for reception of such frequencies according to interrogation at such frequencies in sequence, means for detecting each frequency shift change of such interrogation frequency to a subsequent one of the other frequencies, and means for retuning the resonant circuit for reception of each of such other frequencies whereby to generate frequency shift data bit signals in a format identical to a frequency shift-keying RF format received. 
     
     
       2. A self-tuning receiver/decoder according to claim 1 wherein the means for detecting each frequency shift change of such interrogation frequency to a subsequent one of multiple other frequencies comprises threshold detecting means for determining if received signal strength falls below a predetermined threshold for providing indication of a possible new transmitter frequency. 
     
     
       3. A self-tuning receiver/decoder according to claim 2 wherein the threshold detecting means is a limiter/clipper circuit for receiving signals from the resonant circuit for providing an output signal. 
     
     
       4. A self-tuning receiver/decoder according to claim 1 wherein the means for retuning the resonant circuit comprises counter circuitry for counting through a sequence representing a plurality of more than two transmitter frequency changes in a sequence corresponding to the frequency shift-keying RF format received. 
     
     
       5. A self-tuning receiver/decoder according to claim 1 wherein the resonant circuit is successively tunable to each of a plurality of four frequencies according to a predetermined sequence. 
     
     
       6. A self-tuning receiver/decoder according to claim 5 wherein four frequencies may be represented as f 0 , f 1 , f 2 , f 3  having the relationship f 0  >f 1  >f 2  >f 3  and the predetermined sequence may be represented accordingly by the typical sequence . . . f 2 , f 3 , f 0 , f 1 , f 2 ,f 3 , f 0 , f 1  . . . . 
     
     
       7. A self-tuning receiver/decoder according to claim 4 wherein the counter means comprises a 2-bit counter which is operative for counting through a sequence corresponding to a predetermined sequence of four frequencies f 0 , f 1 , f 2 , f 3  having the relationship f 0  >f 1  >f 2  >f 3 , the means for detecting a each frequency shift change arresting counting of the 2-bit counter and for causing transferring of a pair of data bits upon retuning of the resonant circuit for each received such frequency, and for thereafter reinitiating counting of the 2-bit counter upon the resonant circuit not receiving such frequency. 
     
     
       8. A self-tuning receiver/decoder according to claim 7 wherein the counter means comprises a divide-by-N counter for dividing the received frequency f n  by a factor N for providing count pulses for counting by the 2-bit counter when enabled at a rate f n  /N. 
     
     
       9. A self-tuning receiver/decoder according to claim 8 further comprising a sine-to-square wave converter for providing signals received by the resonant circuit to the divide-by-N counter. 
     
     
       10. A self-tuning receiver/decoder according to claim 7 further comprising signal power loss detector and time delay means for resetting the 2-bit counter to an all-zero condition for initializing the receiver/decoder after a predetermined interval following loss of received signal. 
     
     
       11. A self-tuning receiver/decoder according to claim 1 wherein the receiver/decoder is powered by capacitively stored charge in response to continuous transmission of a selected one of said frequencies for some fixed period of time. 
     
     
       12. A self-tuning receiver/decoder according to claim 10 wherein the selected one of said frequencies is the highest f 0  of four frequencies which may be represented as f 0 , f 1 , f 2 , f 3  having the relationship f 0  >f 1  >f 2  >f 3 , and the resonant circuit is initially tuned for resonance at the highest frequency f 0 . 
     
     
       13. A self-tuning receiver/decoder according to claim 11 wherein the means for retuning the resonant circuit for reception of each of such other frequencies comprises multiple additional capacitance, and semiconductor switch means for selectively switching the additional capacitance combinatively in or out of the resonant circuit for retuning thereof in accordance with a predetermined data sequence. 
     
     
       14. A self-tuning receiver/decoder according to claim 13 wherein the semiconductor switch means is selectively responsive to the counter circuitry during a receive mode of the receiver/decoder and to transmit-mode switching control means during a transmit mode thereof. 
     
     
       15. A self-tuning receiver/decoder according to claim 12 further comprising latch means for providing the predetermined data sequence as an output of the receiver/decoder for representing said frequency shift data bit signals. 
     
     
       16. A self-tuning receiver/decoder according to claim 14 further comprising a 2-bit counter which is operative for counting through a sequence corresponding to the predetermined sequence of said frequencies, the semiconductor switch means comprise MOSFET devices for selectively switching in and out of the resonant circuit respective additional capitances for retuning of the resonant circuit to different ones of said frequencies in response to the 2-bit counter, counting of the 2-bit counter being arrested on tuning of the resonant circuit to a different received one of said frequencies and for causing transferring of a pair of data bits upon retuning of the resonant circuit for each received such frequency, and for thereafter reinitiating counting of the 2-bit counter upon the resonant circuit not receiving such frequency.