Method of setting the output current of a monolithic integrated pad driver

Abstract

The invention is a method and circuit for improving the settability of the output current (i1) of at least one pad driver (D: D1, D2, . . . Dn) to reduce interfering voltage dips on the supply lines. The pulselike current peaks caused by rapid charging/discharging of high load capacitances (c) are particularly avoided. To this end, the respective output transistor (t1, t1') is operated as a current-controlled element in a first range (b1) of the output voltage (OUR) and as a voltage-controlled element in a second range (b2).

We claim: 
     
       1. An improvement in a method of setting an output current of a pad driver (D: D1, D2, . . . Dn) comprising the steps of: operating an output transistor as a current-controlled element in a first range of an output voltage (OUR); and   subsequently operating said output transistor as a voltage-controlled element in a second range,   where said step of operating said output transistor as said current-controlled element in said first range comprises the step of:   driving a control electrode of said output transistor, which is coupled to a control input of said pad driver, in the first range by means of a current mirror (m) whose input is fed from a current source and whose output is formed by the output transistor;   and where subsequently operating said output transistor as a voltage-controlled element in said second range comprises the steps of:   disabling a control electrode of the output transistor in the second range, which output transistor is coupled directly to the control input of said pad driver, and   disabling the current-mirror input with respect to the control input of said pad driver.   
     
     
       2. An improvement in a method of setting an output current of a pad driver (D: D1, D2, . . . Dn) comprising the steps of: operating an output transistor as a current-controlled element in a first range of an output voltage (OUR); and   subsequently operating said output transistor as a voltage-controlled element in a second range,   wherein said steps of operating comprises the step of changing-over from a current-controlled mode in said first range to a voltage-controlled mode in said second range of the output transistor by operation of a switching circuit using a feedback signal (f) dependent on the output voltage (OUR), an input-current path of a current mirror (m) being electrically disconnected from a control input of said pad driver by said switching circuit in said second range, wherein a control electrode of the output transistor is electrically connected to the control input of said pad driver in said second range, and wherein the first and second ranges are set by a switching threshold of the switching circuit.   
     
     
       3. The method of claim 1 wherein said step of operating comprises the step of changing-over from a current-controlled mode to a voltage-controlled mode of the output transistor by electronic switching in a switching circuit using a feedback signal (f) dependent on the output voltage (OUR), said input current source and said current mirror (m) being separated from the control input, wherein the control electrode of the output transistor is connected to the control input, and wherein the first and second ranges are set by a switching threshold of the switching circuit. 
     
     
       4. The method of claim 2 wherein the step of operating comprises the step of delaying the feedback signal (f) with respect to the output voltage (OUR) by means of a delay stage circuit which provides a delay (T) shorter than the pulse transition time of the output voltage (OUR). 
     
     
       5. The method of claim 3 wherein the step of operating comprises the step of delaying the feedback signal (f) with respect to the output voltage (OUR) by means of a delay stage circuit which provides sa delay (T) shorter than the pulse transition time of the output voltage (OUR). 
     
     
       6. The method of claim 3 wherein the step of electronic switching comprises the steps of: coupling a current input of the current mirror (m) to a second transistor which is connected to the control input via a switching transistor;   coupling a delay signal from a delay stage circuit to a control electrode of the switching transistor, and   coupling signals from the control input on a common control line to the current mirror (m).   
     
     
       7. The method of claim 1 comprising the step of providing at least one saturated field-effect transistor in the current source. 
     
     
       8. The method of claim 2 further comprising the step of: feeding a current source, having at least one transistor with a control electrode, with a current source control voltage coupled to the control electrode from an auxiliary current-source (H).   
     
     
       9. The method of claim 8 comprising the step of determining a level of the current source control voltage by the auxiliary current source (H) by means of a controlled current source. 
     
     
       10. The method of claim 9 comprising the steps of: controlling the controlled current source by a phase-locked loop circuit;   coupling to the phase locked loop circuit a signal corresponding to a charging/discharging period of a simulated load capacitance (cn) in a pad-driver-simulating network (N);   coupling to the phase locked loop circuit a reference signal which is a delay of a clock-delay stage (tv) supplied with a standard clock signal; and   determining a deviation of the charging/discharging period from a set point by means of a phase detector (PD).   
     
     
       11. An apparatus for setting an output current of a pad driver (D; D1; D2, . . . Dn) with a circuit which operates an output transistor as a current-controlled element in a first range of an output voltage (OUR) provided on a node (k) and as a voltage-controlled element in a second range, said circuit comprising: an input of the circuit coupled to the node (k);   an output of the circuit coupled to a control electrode of the output transistor;   an electronic switching circuit controlled by the output voltage (OUR);   at least one current source which is coupled to the control electrode of the output transistor via the electronic switching circuit; and   a current mirror (m) where in the first range the control electrode of the output transistor, which is coupled to a control input, is driven by said current mirror (m) having an input fed from the current source and wherein the apparatus has an output provided by the output transistor, and   in the second range, the control electrode of the output transistor is coupled directly to the control input, and the current-mirror input is disabled with respect to the control input.   
     
     
       12. The apparatus of claim 11 wherein change-over from a current-controlled mode to a voltage-controlled mode of the output transistor (t1;t1') is provided by means of a switching circuit and a feedback signal (f) dependent on the output voltage (OUR), an input-current path of the current mirror (m) being electrically separated from the control input; the control electrode of the output transistor being connected to the control input; and   the first and second ranges being set by a switching threshold of the switching circuit.   
     
     
       13. The apparatus of claim 12 wherein the feedback signal (f) is delayed with respect to the output voltage (OUR) by means of a delay stage circuit which provides a delay (T) shorter than the pulse transition time of the output voltage (OUR). 
     
     
       14. The apparatus of claim 13 wherein the switching circuit comprises: a current input of the current mirror (m), which is formed by a second transistor, is connected to the control input via a switching transistor;   wherein the control electrode of the switching transistor is supplied with the output from the delay stage circuit; and   a common control line of the current mirror (m) is coupled to the control input.   
     
     
       15. The apparatus of claim 11 wherein the current source comprises at least one saturated field-effect transistor. 
     
     
       16. The apparatus of claim 12 further comprising an auxiliary current-source (H) and wherein the current source comprises at least one transistor having a control electrode fed with a current source control voltage from the auxiliary current-source (H). 
     
     
       17. The apparatus of claim 16 wherein the current source is a controlled current source controlled by the auxiliary current source (H) which determines the level of the current source control voltage. 
     
     
       18. The apparatus of claim 17 comprises: a simulated load capacitance (cn);   a pad-driver-simulating network (N); and   wherein the controlled current source comprises: a phase-locked loop circuit controlled by a charging/discharging period of the simulated load capacitance (cn) in the pad-driver-simulating network (N);   a clock-delay stage circuit for delaying a standard clock signal, tile clock-delay stage circuit for providing a reference signal to the phase locked loop circuit; and   a phase detector (PD) for determining the deviation of said charging/discharging period from a set point, the phase detector (PD) having inputs coupled to outputs of the clock-delay stage circuit and the pad-driver-simulating network (N).