Horizontal line counter insensitive to large phase shifts of video

Abstract

A horizontal line counter (110,115,120) provides a signal (LINE #21) identifying the beginning of video data in a particular horizontal video line. The counter is clocked by multiple clock signals. A first clock signal (HOR PLS) clocks the counter until the line count value equals a known value that is less than the line number of the horizontal line that is to be identified. When the count value equals the known value, clocking by a second clock signal (COMP SYNC) is enabled. Although, the first clock source provides a regular pulse waveform suitable for clocking the counter reliably, transitions on the first clock signal may not accurately indicate the beginning of information within a horizontal line interval. Transitions on the second clock signal accurately indicate the beginning of the desired information. However, the waveform of the second clock signal may exhibit irregularities prior to the time at which clocking by the second clock signal is enabled that could adversely affect the reliability of the counter value. The combined clocking arrangement advantageously provides significantly higher reliability of the count value and improves the timing of the line identification signal with respect to the beginning of the desired video data.

I claim: 
     
       1. Apparatus for processing a video signal having a vertical display interval including a plurality of horizontal display intervals, said apparatus comprising: means for producing a first pulse waveform including pulses occurring at a rate related to a frequency of occurrence of said horizontal display intervals, each of said pulses included in said first pulse waveform being subject to exhibiting a phase error with respect to the beginning of a respective one of said horizontal display intervals;   means for producing a second pulse waveform including pulses synchronized with respective ones of said horizontal display intervals for indicating the beginning of each of said horizontal display intervals; and   means for counting said horizontal display intervals during a first portion of said vertical display interval in response to said first pulse waveform, and for counting in response to said second pulse waveform during a second portion of said vertical display interval; wherein   said second portion of said vertical display interval beginning in response to a predetermined number of said horizontal display intervals being counted during said first portion of said vertical interval.   
     
     
       2. Apparatus according to claim 1, wherein said first portion of said vertical display interval including a first one of said horizontal display intervals through a twentieth one of said horizontal display intervals.   
     
     
       3. Apparatus according to claim 1, wherein said first portion of said vertical display interval including a first one of said horizontal display intervals through a horizontal display interval penultimate to a predetermined one of said horizontal display interval.   
     
     
       4. Apparatus according to claim 1, wherein said means for producing said first pulse waveform comprises a phase locked loop circuit, and said means for producing said second pulse waveform comprises a sync separator circuit responsive to said video signal.   
     
     
       5. Apparatus according to claim 1, wherein said pulses included in said first pulse waveform exhibiting substantially uniform pulse amplitudes during said first portion of said vertical display interval; and   said pulses included in said second pulse waveform being subject to exhibiting varying pulse amplitudes during said first portion of said vertical display interval.   
     
     
       6. Apparatus for processing a video signal having a vertical display interval including a plurality of horizontal display intervals, said apparatus comprising: means for producing a first clock signal including pulses occurring at a rate related to a frequency of occurrence of said horizontal display intervals, each of said pulses included in said first clock signal being subject to exhibiting a phase error with respect to the beginning of a respective one of said horizontal display intervals;   means for producing a second clock signal including pulses synchronized with respective ones of said horizontal display intervals for indicating the beginning of each of said horizontal display intervals;   means for counting said horizontal display intervals in response to said first clock signal, and for generating a control signal indicating occurrence of a first predetermined one of said horizontal display intervals; and   means responsive to said second clock signal for delaying said control signal to produce a delayed signal exhibiting a desired timing relationship to a second predetermined one of said horizontal display intervals.   
     
     
       7. Apparatus according to claim 6, wherein said pulses included in said first clock signal exhibiting substantially uniform pulse amplitudes during a portion of said vertical display interval in which said counting means counts responsive to said first clock signal; and   said pulses included in said second clock signal being subject to exhibiting varying pulse amplitudes during said portion of said vertical display interval.   
     
     
       8. Apparatus according to claim 7, wherein said means for producing said first clock signal comprises a phase locked loop circuit; and   said means for producing said second clock signal comprises a sync separator circuit.   
     
     
       9. Apparatus according to claim 8, wherein said delaying means comprises a D-type flip-flop having a data input coupled to receive said control signal produced by said counting means, and having a clock input coupled to receive said second clock signal. 
     
     
       10. Apparatus for decoding closed caption data included in one of a plurality of horizontal display intervals included in a vertical display interval of a video signal, said apparatus comprising: means for producing a first clock signal including pulses occurring at a rate related to a frequency of occurrence of said horizontal display intervals, each of said pulses included in said first clock signal being subject to exhibiting a phase error with respect to the beginning of a respective one of said horizontal display intervals;   means for producing a second clock signal including pulses synchronized with respective ones of said horizontal display intervals for indicating the beginning of each of said horizontal display intervals;   means for counting said horizontal display intervals in response to said first clock signal, and for generating a control signal indicating occurrence of one of said horizontal display intervals preceding said horizontal line interval including said closed caption data; and   means responsive to said second clock signal for delaying said control signal to produce a delayed signal exhibiting a desired timing relationship to a beginning of said horizontal display interval including said closed caption data.   
     
     
       11. Apparatus according to claim 10, wherein said pulses included in said first clock signal exhibiting substantially uniform pulse amplitudes during a portion of said vertical display interval in which said counting means counts responsive to said first clock signal; and   said pulses included in said second clock signal being subject to exhibiting varying pulse amplitudes during said portion of said vertical display interval.   
     
     
       12. Apparatus according to claim 11, wherein said means for producing said first clock signal comprises a phase locked loop circuit; and   said means for producing said second clock signal comprises a sync separator circuit.   
     
     
       13. Apparatus according to claim 12, wherein said delaying means comprises a D-type flip-flop having a data input coupled to receive said control signal produced by said counting means, and having a clock input coupled to receive said second clock signal.