Multilayer LTCC tub architecture for hermetically sealing semiconductor die, external electrical access for which is provided by way of sidewall recesses

Abstract

A packaging assembly for a semiconductor circuit chip is formed of a hermetically sealable, `tub`-like structure. The tub-like structure is comprised a laminated stack of thin layers of low temperature co-fired ceramic (LTCC) material. The laminated stack of LTCC layers contains an internally distributed network of interconnect links through which a semiconductor die, that has been mounted at a floor portion of the tub, may be electrically connected to a plurality of conductive recesses or pockets located at top and bottom sidewall edge portions of the tub, thereby allowing multiple tubs to be joined together as a hermetically sealed assembly and electrically interconnected at the conductive pockets of adjacent tubs.

What is claimed: 
     
       1. A packaging device for a semiconductor circuit chip comprising: a floor member having a mounting surface portion upon which a semiconductor circuit chip is mountable; and   a wall member surrounding and adjoining said floor member, so as to form therewith a tub-like structure, such that a semiconductor circuit chip mounted upon said mounting surface portion of said floor member is surrounded by said wall member, said wall member being comprised of an inner wall member portion adjacent to said mounting surface portion and extending a first height above said floor member, and an outer wall member portion adjoining said inner wall member and extending a second height above said floor member, greater than said first height,   said inner wall member portion having one or more first contact regions formed on a first, top surface portion thereof, so that said one or more first contact regions may be electrically connectable to a semiconductor circuit chip mounted on the adjacent mounting surface region of said floor member,   said outer wall member portion having one or more first recesses, at which one or more respective second contact regions are formed, said one or more first recesses extending from an outer edge of a top surface thereof along an outer sidewall of said outer wall member portion a first distance, which terminates and is thereby spaced above a bottom surface of said outer wall member portion, and one or more second recesses, aligned, along said outer sidewall of said outer wall member portion, with said one or more first recesses at which second recesses, one or more respective third contact regions are formed, said one or more second recesses extending from an outer edge of a bottom surface portion of said outer wall member along said outer sidewall of said outer wall member portion a second distance, which terminates and is thereby spaced below said top surface of said outer wall member portion, such that said one or more second recesses do not intersect said one or more first recesses aligned therewith,   said wall member further including an electrical interconnection network which extends between said one or more first contact regions and said one or more second and third contact regions.     
     
     
       2. A packaging device, for a semiconductor circuit chip comprising: a floor member having a mounting surface portion upon which a semiconductor circuit chip is mountable; and   a wall member surrounding and adjoining said floor member, so as to form therewith a tub-like structure, such that a semiconductor circuit chip mounted upon said mounting surface portion of said floor member is surrounded by said wall member, said wall member being comprised of an inner wall member portion adjacent to said mounting surface portion and extending a first height above said floor member, and an outer wall member portion adjoining said inner wall member and extending a second height above said floor member, greater than said first height,   said inner wall member portion having one or more first contact regions formed on a first, top surface portion thereof, so that said one or more first contact regions may be electrically connectable to a semiconductor circuit chip mounted on the adjacent mounting surface region of said floor member,   said outer wall member portion having one or more first recesses, at which one or more respective second contact regions are formed, said one or more first recesses extending from an outer edge of a top surface thereof to a first prescribed depth along an outer sidewall thereof, and one or more second recesses, at which one or more respective third contact regions are formed, said one or more second recesses extending from an outer edge of a bottom surface portion of said outer wall member to a second depth along said outer sidewall,   said wall member further including an electrical interconnection network which extends between said one or more first contact regions and said one or more second and third contact regions, and   wherein said floor member is formed of one or more of a plurality of dielectric layers, and wherein said wall member is comprised of one or more of said plurality of dielectric layers disposed on and laminated together with the one or more layers of said floor member, with a bottom surface of a bottom one of said plurality of dielectric layers defining the bottom surface of said outer wall member, and a top surface of a top one of said plurality of dielectric layers defining the top surface of said outer wall member.     
     
     
       3. A package assembly according to claim 2, wherein said inner wall member portion is formed of one or more of said plurality of dielectric layers disposed on said floor member, and said outer wall member portion is formed of one or more of said plurality of dielectric layers disposed on said inner wall member. 
     
     
       4. A package assembly according to claim 3, wherein said electrical interconnection network comprises one or more conductive vias which extend through one or more layers of said wall member, and conductive layers disposed on selected ones of said plurality of dielectric layers and being electrically connected to said one or more conductive vias and said one or more first, second and third contact regions. 
     
     
       5. A package assembly according to claim 4, wherein said dielectric layers comprise low temperature co-fired ceramic layers. 
     
     
       6. A packaging device, for a semiconductor circuit chip comprising: a floor member having a mounting surface portion upon which a semiconductor circuit chip is mountable; and   a wall member surrounding and adjoining said floor member, so as to form therewith a tub-like structure, such that a semiconductor circuit chip mounted upon said mounting surface portion of said floor member is surrounded by said wall member, said wall member being comprised of an inner wall member portion adjacent to said mounting surface portion and extending a first height above said floor member, and an outer wall member portion adjoining said inner wall member and extending a second height above said floor member, greater than said first height,   said inner wall member portion having one or more first contact regions formed on a first, top surface portion thereof, so that said one or more first contact regions may be electrically connectable to a semiconductor circuit chip mounted on the adjacent mounting surface region of said floor member,   said outer wall member portion having one or more first recesses, at which one or more respective second contact regions are formed, said one or more first recesses extending from an outer edge of a top surface thereof to a first prescribed depth along an outer sidewall thereof, and one or more second recesses, at which one or more respective third contact regions are formed, said one or more second recesses extending from an outer edge of a bottom surface portion of said outer wall member to a second depth along said outer sidewall,   said wall member further including an electrical interconnection network which extends between said one or more first contact regions and said one or more second and third contact regions, and   wherein said floor member and said wall member are formed of a stacked laminate of a plurality of low temperature co-fired ceramic layers.     
     
     
       7. A package assembly according to claim 6, wherein each of said floor member, said inner wall member portion, and said outer wall member portion is formed of plural low temperature co-fired ceramic layers. 
     
     
       8. A package assembly according to claim 1, further including a lid hermetically sealed to the top surface of said wall member. 
     
     
       9. A packaging and interconnect assembly for a plurality of semiconductor circuit chips comprising: a plurality of stacked tub-configured structures, each tub-configured structure including a floor member having a mounting surface portion upon which a semiconductor circuit chip is mountable, and a wall member surrounding and adjoining said floor member, so as to form therewith a tub-configured structure, such that a semiconductor circuit chip mounted upon said mounting surface portion of said floor member is surrounded by said wall member, said wall member being comprised of an inner wall member portion adjacent to said mounting surface portion and extending a first height above said floor member, and an outer wall member portion adjoining said inner wall member and extending a second height above said floor member, greater than said first height,   said inner wall member portion having one or more first contact regions formed on a first, top surface portion thereof, so that said one or more first contact regions may be electrically connectable to a semiconductor circuit chip mounted on the adjacent mounting surface region of said floor member,   said outer wall member portion having one or more first recesses, at which one or more respective second contact regions are formed, said one or more first recesses extending from an outer edge of a top surface thereof to a first prescribed depth along an outer sidewall thereof, and one or more second recesses, at which one or more respective third contact regions are formed, said one or more second recesses extending from an outer edge of a bottom surface portion of said outer wall member to a second depth along said outer sidewall,   said wall member further including an electrical interconnection network which extends between said one or more first contact regions and said one or more second and third contact regions; and wherein     said plurality of tub-configured structures are stacked atop one another such that the bottom surface of the outer wall member portion of one tub-configured structure is disposed upon the top surface of an outer wall member portion of another tub-configured structure, so that a second recess of the outer wall member portion of said one tub-configured structure is adjacent to a first recess of the outer wall member portion of said another tub-configured structure, and wherein conductive material is provided at selected adjacent first and second recesses, so as to electrically connect electrical interconnect networks of selected one and another tub-configured structures, and thereby provide electrical interconnections between selected semiconductor circuit chips mounted in the tub-configured structures of said stack.   
     
     
       10. A packaging and interconnect assembly according to claim 9, wherein a floor member of a respective tub-configured structure is formed of one or more of a plurality of dielectric layers, and wherein said wall member is comprised of one or more of said plurality of dielectric layers disposed on and laminated together with the one or more layers of said floor member, with a bottom surface of a bottom one of said plurality of dielectric layers defining the bottom surface of said outer wall member, and a top surface of a top one of said plurality of dielectric layers defining the top surface of said outer wall member. 
     
     
       11. A packaging and interconnect assembly according to claim 10, wherein said inner wall member portion is formed of one or more of said plurality of dielectric layers disposed on said floor member, and said outer wall member portion is formed of one or more of said plurality of dielectric layers disposed on said inner wall member. 
     
     
       12. A packaging and interconnect assembly according to claim 11, wherein said electrical interconnection network comprises one or more conductive vias which extend through one or more layers of said wall member, and conductive layers disposed on selected ones of said plurality of dielectric layers and being electrically connected to said one or more conductive vias and said one or more first, second and third contact regions. 
     
     
       13. A packaging and interconnect assembly according to claim 12, wherein said dielectric layers comprise low temperature co-fired ceramic layers. 
     
     
       14. A packaging and interconnect assembly according to claim 9, wherein said floor member and said wall member are formed of a stacked laminate of a plurality of low temperature co-fired ceramic layers. 
     
     
       15. A packaging and interconnect assembly according to claim 14, wherein each of said floor member, said inner wall member portion, and said outer wall member portion is formed of plural low temperature co-fired ceramic layers. 
     
     
       16. A packaging and interconnect assembly according to claim 9, further including a lid hermetically sealed to the top surface of the outer wall member portion of a topmost one of the stacked tub-configured structures. 
     
     
       17. A packaging and interconnect assembly according to claim 9, wherein said plurality of tub-configured structures are stacked atop one another with respective layers of hermetically sealing material between successive tub-configured structures, such that the bottom surface of the outer wall member portion of one tub-configured structure is joined with a hermetically sealing material disposed upon the top surface of an outer wall member portion of another tub-configured structure.