Interface circuit for controlling data transfers

Abstract

An interface circuit for a peripheral device is disclosed that can accurately cope with any host with the same hardware whether the host is in the pre-read mode or the post-read mode and can send an interrupt request to the host practically without a waiting time if the host is in the post-read mode. The interface circuit generates an interrupt request (IRQ) to a host in response to a data request (DRQ) from a peripheral device (HDD) and drops the interrupt request if the status of the peripheral device is read by the host; it detects that the host operates in a post-read mode, and responds to the post-read mode detect signal and the status reading by the host in order to enable the regeneration of the interrupt request to the host.

What is claimed is: 
     
       1. In a computer system in which a peripheral device generates a data request to send an interrupt request to a host when a block of data is ready to be transferred, and the host responds to said interrupt request and operates in one of a first mode to start a block data transfer after reading status of said peripheral device or in a second mode to read said status after completing said block data transfer, an interface circuit for controlling data transfers, comprising: interrupt means for generating said interrupt request in response to said data request and dropping said interrupt request in response to said status reading;   mode detecting means for detecting that said host operates in said second mode to read said status after completing said block data transfer; and   interrupt enable means responsive to a second mode detect signal from said mode detecting means and said status reading to enable said interrupt means to regenerate said interrupt request.   
     
     
       2. The interface circuit of claim 1, wherein said data request is dropped at the completion of reading said block of data and regenerated when the next block of data is ready to be transferred. 
     
     
       3. The interface circuit of claim 2, wherein said interrupt means includes a first flip-flop which is set in response to the generation of said data request and the output of said flip-flop becomes said interrupt request. 
     
     
       4. The interface circuit of claim 3, wherein said mode detecting means includes a second flip-flop which is set to the same condition as said first flip-flop in response to said data request. 
     
     
       5. The interface circuit of claim 4, wherein said interrupt enable means includes a third flip-flop which is set to the same condition as said second flip-flop in response to said status reading, a counter which starts counting in response to the setting of said third flip-flop, a register into which a predetermined delay value is loaded, and a comparator which compares the contents of said counter and said register and, when they are equal to each other, sets said first flip-flop and resets said second flip-flop and said third flip-flop. 
     
     
       6. The interface circuit of claim 5, wherein said delay value is set so that said interrupt request can be generated when said host is ready to respond. 
     
     
       7. A computer system, comprising: a host;   a peripheral device connected to said host; and   an interface circuit in said peripheral device for controlling data transfers, said interface circuit generates a data request to send an interrupt request to said host when a block of data is ready to be transferred, and said host responds to said interrupt request and operates in one of a first mode to start a block data transfer after reading status of said peripheral device or in a second mode to read said status after completing said block data transfer;   interrupt means for generating said interrupt request in response to said data request and dropping said interrupt request in response to said status reading;   mode detecting means for detecting that said host operates in said second mode; and   interrupt enable means responsive to a second mode detect signal from said mode detecting means and said status reading to enable said interrupt means to regenerate said interrupt request.   
     
     
       8. The computer system of claim 7, wherein said data request is dropped at the completion of reading said block of data and regenerated when the next block of data is ready to be transferred. 
     
     
       9. The computer system of claim 8, wherein said interrupt means includes a first flip-flop which is set in response to the generation of said data request and the output of said flip-flop becomes said interrupt request. 
     
     
       10. The computer system of claim 9, wherein said mode detecting means includes a second flip-flop which is set to the same condition as said first flip-flop in response to said data request. 
     
     
       11. The computer system of claim 10, wherein said interrupt enable means includes a third flip-flop which is set to the same condition as said second flip-flop in response to said status reading, a counter which starts counting in response to the setting of said third flip-flop, a register into which a predetermined delay value is loaded, and a comparator which compares the contents of said counter and said register and, when they are equal to each other, sets said first flip-flop and resets said second flip-flop and said third flip-flop. 
     
     
       12. The computer system of claim 11, wherein said delay value is set so that said interrupt request can be generated when said host is ready to respond. 
     
     
       13. A method in a computer system for a peripheral device to generate a data request to send an interrupt request to a host when a block of data is ready to be transferred, and the host to respond to said interrupt request and operate in one of a first mode to start a block data transfer after reading status of said peripheral device or in a second mode to read said status after completing said block data transfer, comprising the steps of: generating said interrupt request in response to said data request and dropping said interrupt request in response to said status reading;   detecting that said host operates in said second mode to read said status after completing said block data transfer; and   responding to a second mode detect signal from said detecting step and said status reading to enable said generating step to regenerate said interrupt request.   
     
     
       14. The method of claim 13, wherein said data request is dropped at the completion of reading said block of data and regenerated when the next block of data is ready to be transferred. 
     
     
       15. The method of claim 14, wherein said generating step uses a first flip-flop which is set in response to the generation of said data request and the output of said flip-flop becomes said interrupt request. 
     
     
       16. The method of claim 15, wherein said detecting step uses a second flip-flop which is set to the same condition as said first flip-flop in response to said data request. 
     
     
       17. The method of claim 16, wherein said detecting step uses a third flip-flop which is set to the same condition as said second flip-flop in response to said status reading, a counter which starts counting in response to the setting of said third flip-flop, a register into which a predetermined delay value is loaded, and a comparator which compares the contents of said counter and said register and, when they are equal to each other, sets said first flip-flop and resets said second flip-flop and said third flip-flop. 
     
     
       18. The method of claim 17, wherein said delay value is set so that said interrupt request can be generated when said host is ready to respond. 
     
     
       19. A peripheral device that generates a data request to send an interrupt request to a host when a block of data is ready to be transferred, and the host responds to said interrupt request and operates in one of a first mode to start a block data transfer after reading status of said peripheral device or in a second mode to read said status after completing said block data transfer, an interface circuit for controlling data transfers, said peripheral device comprising: interrupt means for generating said interrupt request in response to said data request and dropping said interrupt request in response to said status reading;   mode detecting means for detecting that said host operates in said second mode to read said status after completing said block data transfer; and   interrupt enable means responsive to a second mode detect signal from said mode detecting means and said status reading to enable said interrupt means to regenerate said interrupt request.   
     
     
       20. The peripheral device of claim 19, wherein said data request is dropped at the completion of reading said block of data and regenerated when the next block of data is ready to be transferred. 
     
     
       21. The peripheral device circuit of claim 20, wherein said interrupt means includes a first flip-flop which is set in response to the generation of said data request and the output of said flip-flop becomes said interrupt request. 
     
     
       22. The peripheral device of claim 21, wherein said mode detecting means includes a second flip-flop which is set to the same condition as said first flip-flop in response to said data request. 
     
     
       23. The peripheral device of claim 22, wherein said interrupt enable means includes a third flip-flop which is set to the same condition as said second flip-flop in response to said status reading, a counter which starts counting in response to the setting of said third flip-flop, a register into which a predetermined delay value is loaded, and a comparator which compares the contents of said counter and said register and, when they are equal to each other, sets said first flip-flop and resets said second flip-flop and said third flip-flop. 
     
     
       24. The peripheral device of claim 23, wherein said delay value is set so that said interrupt request can be generated when said host is ready to respond.