Masked radiant anneal diffusion method

Abstract

Only the areas of the CdTe/HgCdTe interface of a FPA detector circuit which is coupled by an epoxy to a silicon-based integrated circuit that require interdiffusing are heated to a sufficiently high temperature or have photons of light impinging thereon for a sufficient time to cause interdiffusion of the two layers by the travel of tellurium into the HgCdTe and the travel of mercury into the CdTe. The vast majority of the wafer is masked with an aluminum thin film to greatly reduce heat gain or photon transmission. An advantage of the process in accordance with the present invention is that only a very small fraction of the HgCdTe/epoxy/silicon-based integrated circuit wafer receives incoming energy during interdiffusion whereby problems caused by the differences in coefficient of thermal expansion between silicon and HgCdTe at the epoxy interface are minimized.

We claim: 
     
       1. A method of fabricating a semiconductor device comprising the steps of: (a) providing a group II-VI semiconductor wafer having a surface and a passivating layer disposed over said surface to form an interface with said wafer with said passivating layer having an exposed surface opposed to said interface;   (b) masking a region of said exposed surface of said passivating layer with one of a heat energy reflecting layer or a non-photon-transmitting layer with the remainder of said exposed surface being an unmasked region; and   (c) causing interdiffusion of said group II-VI semiconductor wafer and said passivating layer disposed only at said interface of said semiconductor wafer and said passivating layer in said unmasked region by impinging heat energy upon the masked and unmasked regions of said passivating layer when a heat energy reflecting layer is used in step (b) or by impinging light energy upon the masked and unmasked regions of said passivating layer when a non-photon-transmitting layer is used in step (b), the energy impinging upon the mask being reflected therefrom.   
     
     
       2. The method of claim 1 wherein said group II-VI semiconductor wafer is HgCdTe. 
     
     
       3. The method of claim 1 wherein said step of masking comprises masking with a layer of aluminum. 
     
     
       4. The method of claim 2 wherein said step of masking comprises masking with a layer of aluminum. 
     
     
       5. The method of claim 1 further including the step of disposing a layer of a material over said passivating layer prior to step (b) having a band gap higher than said group II-VI semiconductor wafer. 
     
     
       6. The method of claim 4 further including the step of disposing a layer of a material over said passivating layer prior to step (b) having a band gap higher than said group II-VI semiconductor wafer. 
     
     
       7. The method of claim 1 wherein said passivating layer is a group II-VI material with a higher band gap than said group II-VI semiconductor wafer. 
     
     
       8. The method of claim 1 wherein said passivating layer is from about 100 angstroms to about 2000 angstroms thick. 
     
     
       9. The method of claim 2 wherein said passivating layer is a group II-VI material with a higher band gap than said group II-VI semiconductor wafer. 
     
     
       10. The method of claim 2 wherein said passivating layer is from about 100 angstroms to about 2000 angstroms thick. 
     
     
       11. The method of claim 4 wherein said passivating layer is a group II-VI material with a higher band gap than said group II-VI semiconductor wafer. 
     
     
       12. The method of claim 4 wherein said passivating layer is from about 100 angstroms to about 2000 angstroms thick. 
     
     
       13. The method of claim 8 wherein said passivating layer is a group II-VI material with a higher band gap than said group II-VI semiconductor wafer. 
     
     
       14. The method of claim 7 wherein said passivating layer is from about 100 angstroms to about 2000 angstroms thick. 
     
     
       15. The method of claim 1 wherein said passivating layer is CdTe. 
     
     
       16. The method of claim 2 wherein said passivating layer is CdTe. 
     
     
       17. The method of claim 4 wherein said passivating layer is CdTe. 
     
     
       18. The method of claim 8 wherein said passivating layer is CdTe. 
     
     
       19. A method of fabricating a semiconductor device comprising the steps of: (a) providing a group II-VI semiconductor wafer having a surface and a passivating layer disposed over said surface to form an interface with said passivating layer, said passivating layer having an exposed surface opposed to said interface;   (b) masking with a mask a region of said exposed surface of said passivating layer with an energy reflecting layer with the remainder of said exposed surface being an unmasked region; and   (c) impinging energy upon the masked and unmasked regions of said passivating layer, the energy impinging upon the mask being reflected therefrom, to cause interdiffusion of said group II-VI semiconductor and said passivating layer at said unmasked region.   
     
     
       20. The method of claim 19 wherein said group II-VI semiconductor wafer is HgCdTe. 
     
     
       21. The method of claim 19 wherein said step of masking with an energy reflecting layer comprises masking with a layer of aluminum. 
     
     
       22. The method of claim 20 wherein said step of masking with an energy reflecting layer comprises masking with a layer of aluminum. 
     
     
       23. The method of claim 19 further including the step of disposing a layer of zinc sulfide over said passivating layer prior to step (b). 
     
     
       24. The method of claim 20 further including the step of disposing a layer of zinc sulfide over said passivating layer prior to step (b). 
     
     
       25. The method of claim 20 wherein said passivating layer is CdTe. 
     
     
       26. The method of claim 22 wherein said passivating layer is CdTe. 
     
     
       27. The method of claim 1 wherein said passivating layer is a group II-VI compound having a band gap greater than that of HgCdTe. 
     
     
       28. The method of claim 1 further including the step of providing a silicon-based wafer containing an integrated circuit secured to said group II-VI semiconductor wafer.