Method of fabricating a semiconductor device with a polycrystalline silicon resistive layer

Abstract

Provided is a novel method of fabricating a polycrystalline silicon layer serving as a resistive element involved in a high frequency semiconductor integrated circuit device. The novel method essentially comprises following steps. A polycrystalline silicon layer is deposited on an insulation layer covering a semiconductor substrate, followed by a selective photo etching by using a photo resist as a mask, and further followed by a selective doping by using ion-implantation with employing a photo resist pattern so as to introduce dopant into the remaining polycrystalline silicon layer except for a peripheral area having a predetermined width thereby resulting in a resistive layer which comprises not only a doped area but an undped area fencing the doped area.

What is claimed is: 
     
       1. A method of fabricating a polycrystalline silicon layer serving as a resistive element involved in a semiconductor integrated circuit device, said method comprising the steps of: depositing a polycrystalline silicon layer on an insulation layer covering a semiconductor substrate;   subjecting said deposited polycrystalline silicon layer to selective doping by using ion-implantation with employing a photo resist pattern; and   subjecting said doped polycrystalline silicon layer to a selective etching by using a photo resist pattern as a mask so as to have said polycrystalline silicon layer remain at not only said doped area but an undoped peripheral area having a width of 0.5 to 1.5 micrometers,   wherein said peripheral area acts as a buffer preventing variation of area, caused by variations in said selective etching, from occurring in a central portion of said polycrystalline silicon layer.   
     
     
       2. The method of fabricating a polycrystalline silicon layer serving as a resistive element as claimed in claim 1, wherein said etching is accomplished by using a photo resist which covers not only said doped area but an undoped peripheral area of said polycrystalline silicon layer. 
     
     
       3. The method of fabricating a polycrystalline silicon layer serving as a resistive element as claimed in claim 1, further comprising the steps of: forming an insulation film so as to cover said doped polycrystalline silicon layer; and   subjecting said covered polycrystalline silicon layer to a heat treatment for dopant activation.   
     
     
       4. The method of fabricating a polycrystalline silicon layer serving as a resistive element as claimed in claim 1, wherein said ion-implantation is accomplished with employing both a photo resist and a conductive metal layer underlying said photo resist, said conductive metal layer serving as a prevention against a charge-up of ions. 
     
     
       5. The method of fabricating a polycrystalline silicon layer serving as a resistive element as claimed in claim 1, wherein said ion-implantation is accomplished with employing both a photo resist and an insulation film underlying said photo resist, said insulation film serving as a prevention against a charge-up of high energy ions. 
     
     
       6. A method of fabricating a high frequency semiconductor integrated circuit device including a polycrystalline silicon layer serving as a resistive element, said method comprising the steps of: forming an active region including at least one active element on a semiconductor substrate;   forming an insulation layer so as to accomplish the isolation of said active element;   forming an insulation film on an entire surface of said device so as to cover both said active region and said insulation layer;   depositing a polycrystalline silicon layer on said insulation film;   subjecting said deposited polycrystalline silicon layer to selective doping by using ion-implantation with employing a photo resist pattern as a mask so that dopant is introduced into a predetermined area over said insulation layer opposite to said active region; and   subjecting said doped polycrystalline silicon layer to a selective etching by using a photo resist pattern as a mask so as to have said polycrystalline silicon layer remain at not only said doped area but an undoped peripheral area having a width of 0.5 to 1.5 micrometers,   wherein said peripheral area acts as a buffer preventing variation of area, caused by variations in said selective etching, from occurring in a central portion of said polycrystalline silicon layer.   
     
     
       7. The method of fabricating a polycrystalline silicon layer serving as a resistive element as claimed in claim 6, wherein said ion-implantation is accomplished with employing a photo resist which covers only said undoped peripheral area of said remaining polycrystalline silicon layer. 
     
     
       8. The method of fabricating a polycrystalline silicon layer serving as a resistive element as claimed in claim 6, further comprising the steps of: forming an insulation film so as to cover said doped polycrystalline silicon layer; and   subjecting said covered polycrystalline silicon layer to a heat treatment for dopant activation.   
     
     
       9. The method of fabricating a polycrystalline silicon layer serving as a resistive element as claimed in claim 8, wherein said heat treatment is accomplished so as to cause not only said dopant activation but a thermal diffusion for forming active elements. 
     
     
       10. The method of fabricating a polycrystalline silicon layer serving as a resistive element as claimed in claim 6, further comprising the steps of: forming contact electrodes of said active element, which comprises polycrystalline silicon after forming said polycrystalline silicon layer serving as a resistive element.