Output drivers in high frequency circuits

Abstract

A high frequency circuit using output drivers with tri-state sections. The plurality of output drivers are connected to an output transmission line. Each driver has a pull-up section, a pull-down section and a tri-state section. Each tri-state section has a low impedance and a high impedance state. Its low impedance state serves to match the impedance of the output transmission line. Its high impedance state isolates its driver from the output transmission line.

I claim: 
     
       1. A high frequency circuit comprising an output driver driving an output transmission line, the output transmission line having a characteristic impedance Zo and having a first and a second end, the driver comprising: a pull-up section connected between a first terminal and a second terminal, the pull-up section responding to an input signal to provide a low impedance current path between the first terminal and the second terminal for establishing a first logic level at the second terminal if the input signal assumes a second logic level, the low impedance current path having an impedance Zd;   a pull-down section connected between a third terminal and the second terminal, the pull-down section responding to the input signal to provide a low impedance current path between the third terminal and the second terminal for establishing the second logic level at the second terminal if the input signal assumes the first logic level, the low impedance current path having an impedance that is substantially equal to Zd; and   a tri-state section, having an output, connected between the second terminal and the first end of the output transmission line, responsive to a control signal to assume one of a high impedance state and a low impedance state, the tri-state section, in its high impedance state, substantially isolating the second terminal from the output transmission line, and the tri-state section, in its low impedance state, coupling the second terminal to the output transmission line through an impedance Zc that is substantially equal to (Zo-Zd).   
     
     
       2. A high frequency circuit as recited in claim 1 further comprising a plurality of output drivers, each output driver being identical to the one in claim 1, all the output drivers driving the output transmission line; wherein, at any given time, only one tri-state section is controlled by its control signal to its low impedance state so that its second terminal is coupled to the output transmission line.   
     
     
       3. A high frequency circuit as recited in claim 2, wherein for each output driver: the pull-up section comprises a PMOS transistor; and   the pull-down section comprises an NMOS transistor.   
     
     
       4. A high frequency circuit as recited in claim 2, wherein for each output driver: the PMOS transistor has a source, a gate and a drain, the source being connected to the first terminal, the drain being connected to the second terminal and the gate receiving the input signal; and   the NMOS transistor has a source, a gate and a drain, the drain being connected to the second terminal, the source being connected to the third terminal and the gate receiving the input signal.   
     
     
       5. A high frequency circuit as recited in claim 2, wherein for each output driver: the pull-up section comprises a CMOS circuit driving a bipolar transistor; and   the pull-down section comprises an NMOS transistor.   
     
     
       6. A high frequency circuit as recited in claim 5, wherein for the pull-up section of each output driver: the bipolar transistor has a collector, a base and an emitter, the collector being connected to the first terminal, and the emitter being connected to the second terminal;   the CMOS circuit comprises: a PMOS transistor with a source, a gate and a drain, the drain being connected to the base of the bipolar transistor, the source being connected to the first terminal and the gate receiving the input signal; and   an NMOS transistor with a source, a gate and a drain, the drain being connected to the base of the bipolar transistor, the source being connected to the third terminal and the gate receiving the input signal; and     the NMOS transistor in the pull-down section has a source, a gate and a drain, the drain being connected to the second terminal, the source being connected to the third terminal and the gate receiving the input signal.   
     
     
       7. A high frequency circuit as recited in claim 2, wherein for each output driver: the pull-up section comprises a CMOS circuit driving a bipolar transistor; and   the pull-down section comprises a plurality of NMOS transistors driving a bipolar transistor.   
     
     
       8. A high frequency circuit as recited in claim 7, wherein for the pull-up section of each output driver: the bipolar transistor has a collector, a base and an emitter, the collector being connected to the first terminal, and the emitter being connected to the second terminal; and   the CMOS circuit comprises: a PMOS transistor with a source, a gate and a drain, the drain being connected to the base of the bipolar transistor, the source being connected to the first terminal and the gate receiving the input signal; and   an NMOS transistor with a source, a gate and a drain, the drain being connected to the base of the bipolar transistor, the source being connected to the third terminal and the gate receiving the input signal; and wherein for the pull-down section of each output driver:       the bipolar transistor has a collector, a base and an emitter, the collector being connected to the second terminal, and the emitter being connected to the third terminal; and   the NMOS transistors comprise: a first NMOS transistor with a drain, a gate and a source, the drain being connected to the second terminal, the gate receiving the input signal and the source being connected to the base of the bipolar transistor; and   a second NMOS transistor with a drain, a gate and a source, the drain being connected to the base of the bipolar transistor, the gate being connected to the base of the bipolar transistor in the pull-up section and the source being connected to the third terminal.     
     
     
       9. A high frequency circuit as recited in claim 2, wherein for each output driver, the tri-state section comprises: a PMOS transistor; and   an NMOS transistor parallel to the PMOS transistor; wherein:     the control signal puts the tri-state section into its low impedance state by setting the impedance of the NMOS transistor to be in a first low impedance state while the complement of the control signal sets the impedance of the PMOS transistor to be in a second low impedance.   
     
     
       10. A high frequency circuit as recited in claim 9, wherein each tri-state section further comprises an inverter, the inverter receiving the control signal of the tri-state section and having an output; and   wherein for each tri-state section: the PMOS transistor has a drain, a gate and a source, its gate being connected to the output of the inverter; and   the NMOS transistor has a drain, a gate and a source, its drain being connected to the drain of the PMOS transistor, its source being connected to the source of the PMOS transistor, and its gate receiving the control signal.     
     
     
       11. A high frequency circuit as recited in claim 1 further comprising: a plurality of output drivers, each output driver being identical to the one in claim 1;   one or more intermediate transmission lines, the intermediate transmission lines connecting the output drivers to the output transmission line, each intermediate transmission line having a characteristic impedance that is substantially equal to Zo, and each intermediate transmission line being connected to at least one output driver; and   for each driver: its input signal has a rise time; and   the time needed for its input signal to propagate through an artificial transmission line with a characteristic impedance of Zo and with a length equal to twice the sum of the lengths of all the intermediate transmission lines is substantially less than the rise time of its input signal.     
     
     
       12. A high frequency circuit as recited in claim 11 wherein for each driver, the time needed for its input signal to propagate through the artificial transmission line is less than half of the fastest rise time of all the input signals.