Insulated gate bipolar transistor provided with a minority carrier extracting layer

Abstract

A p type pad well layer is formed at the surface of an n - type drain layer under a gate bonding pad and the surface thereof is provided with a p ++ type pad layer to be provided with lower resistivity. The p ++ type pad layer is connected with a source electrode through a contact hole. Since the gate electrode supplying each cell with gate potential is of a pattern having extensions in a comb-teeth form arranged along the boundary between the pad region and the cell region, there is present substantially no gate electrode under the pad. Hence, introduction of impurities into the entire surface of the well layer under the pad region can be performed simultaneously with formation of p ++ type contact layers after the formation of the gate electrode, and accordingly, the low resistance p ++ type pad layer can be easily formed. The p ++ type pad layer serves as a low resistance path for allowing the holes flowing into the region under the pad region of the insulated gate bipolar transistor to escape to the source electrode, whereby occurrence of the latch up and increase in the turn-off time due to the minority carriers concentrating into the border portion cell located adjacent to the pad region can be prevented.

What is claimed is: 
     
       1. An insulated gate bipolar transistor comprising: a semiconductor substrate of a first conductivity type;   a semiconductor layer of a second conductivity type located on said substrate, said semiconductor layer having a first region and a second region which shares a border with said first region;   base layers of said first conductivity type located over a surface of said first region of said semiconductor layer;   a well layer of said first conductivity type located over a surface of said second region of said semiconductor layer, said well layer having a junction depth equal to that of said base layers;   source layers of said second conductivity type located in each base layer, each base layer constituting a portion of a respective unit cell region, a junction of each source layer within a corresponding base layer terminating at a surface thereof and at a distance from a junction between said corresponding base layer and the semiconductor layer;   a gate electrode located in said first region such that said gate electrode overlaps at least a channel region with a gate insulating film interposed therebetween, said channel region being formed at a distance away from a surface of said base layer located between said semiconductor layer and said source layer, said gate electrode also being located over a portion of said second region adjacent said border between said first region and said second region such that said gate electrode overlaps only said portion of said well layer adjacent said border;   a source electrode having a first contact portion connected to said corresponding base layer and corresponding source layer in each of said unit cell regions, and a second contact portion connected to a contact region of said well layer; and   a minority carrier extracting layer of said first conductivity type located at a surface of said well layer, said minority carrier extracting layer overlapping virtually an entire area of said well layer and including said second contact portion, said minority carrier extracting layer having an impurity concentration higher than said well layer so as to permit a flowing out of minority carriers, which have flowed from said semiconductor substrate into said second region of said semiconductor layer, into said source electrode.   
     
     
       2. An insulated gate bipolar transistor according to claim 1, further comprising a gate electrode pad electrically connected to said gate electrode, said gate electrode pad being located in said second region over said well layer with an insulating film interposed therebetween; and said insulating film is provided with a first contact hole for electrically connecting said gate electrode pad with said gate electrode and a second contact hole for electrically connecting said minority carrier extracting layer with said source electrode at said contact region,   said first and second contact holes being formed over said well layer so as to be disposed alternately along the border shared by said first region and said second region.   
     
     
       3. An insulated gate bipolar transistor according to claim 2, wherein said gate electrode pad is a gate bonding pad. 
     
     
       4. An insulated gate bipolar transistor according to claim 2, wherein said gate electrode pad is a gate electrode runner metal. 
     
     
       5. An insulated gate bipolar transistor comprising: a semiconductor substrate of a first conductivity type;   a semiconductor layer of a second conductivity type located on said substrate having a first region and a second region which shares a border with said first region;   base layers of said first conductivity type located over a surface of said first region of said semiconductor layer;   source layers of said second conductivity type located in each base layer, each base layer constituting a portion of a respective unit cell region, a junction of each source layer within a corresponding base layer terminating at a surface thereof and at a distance from a junction between said corresponding base layer and the semiconductor layer;   a well layer of said first conductivity type located over the surface of second region of said semiconductor layer, said well layer having a junction depth equal to that of said base layers;   a gate electrode located in said first region such that said gate electrode overlaps at least a channel region with a gate insulating film interposed therebetween, said channel region being formed at a distance away from a surface of said base layer located between said semiconductor layer and said source layer, said gate electrode also being located over a surface of said second region with an insulating film interposed therebetween such that plural extensions of said gate electrode, of a predetermined length, extend in repetitive fashion from a side of said first region to a side of said second region along said border shared by said second region and said first region;   a source electrode having a first contact portion connected to the corresponding base layer and corresponding source layer in each of said unit cell regions, and a second contact portion connected to a contact region of said well layer;   a minority carrier extracting layer of the first conductivity type located at a surface of said well layer, said minority carrier extracting layer overlapping virtually an entire area of said well layer and including said second contact portion, said minority carrier extracting layer having an impurity concentration higher than said well layer so as to permit a flowing out of minority carriers, which have flowed from said semiconductor substrate into said second region of said semiconductor layer, into said source electrode; and   a gate electrode pad having contact portions connected to said plural extensions of said gate electrode and disposed over said minority carrier extracting layer formed at the surface of said well layer.   
     
     
       6. An insulated gate bipolar transistor comprising: a semiconductor substrate of a first conductivity type;   a semiconductor layer of a second conductivity type located on said substrate, said semiconductor layer having a first region and a second region which shares a border with said first region;   base layers of said first conductivity type located over a surface of said first region of said semiconductor layer;   a well layer of said first conductivity type located over a surface of said second region of said semiconductor layer;   source layers of said-second conductivity type located in each base layer, each base layer constituting a portion of a respective unit cell region, a junction of each source layer within a corresponding base layer terminating at a surface thereof and at a distance from a junction between said corresponding base layer and said semiconductor layer;   a gate electrode located in said first region such that said gate electrode overlaps at least a channel region with a gate insulating film interposed therebetween, said channel region being defined by said distance, said gate electrode also being located over a portion of said second region adjacent said border between said first region and said second region such that said gate electrode overlaps only said portion of said well layer adjacent said border;   a source electrode having a first contact portion connected to said corresponding base layer and corresponding source layer in each of said unit cell regions, and a second contact portion connected to a contact region of said well layer; and   a minority carrier extracting layer of said first conductivity type located at a surface of said well layer so as to include said second contact portion, said minority carrier extracting layer having an impurity concentration higher than said well layer so as to permit a flowing out of minority carriers, which have flowed from said semiconductor substrate into said second region of said semiconductor layer, into said source electrode.   
     
     
       7. An insulated gate bipolar transistor according to claim 6 further comprising a gate electrode pad electrically connected to said gate electrode, said gate electrode pad being located in said second region over said well layer with an insulating film interposed therebetween; and said insulating film is provided with a first contact hole for electrically connecting said gate electrode pad with said gate electrode and a second contact hole for electrically connecting said minority carrier extracting layer with said source electrode at said contact region,   said first and second contact holes being formed over said well layer so as to be disposed alternately along the border shared by said first region and said second region.   
     
     
       8. An insulated gate bipolar transistor according to claim 7, wherein said gate electrode pad is a gate bonding pad. 
     
     
       9. An insulated gate bipolar transistor according to claim 8, wherein said gate electrode pad is a gate electrode runner metal. 
     
     
       10. An insulated gate bipolar transistor comprising: a semiconductor substrate of a first conductivity type;   a semiconductor layer of a second conductivity type located on said substrate having a first region and a second region which shares a border with said first region;   base layers of said first conductivity type located over a surface of said first region of said semiconductor layer;   source layers of said second conductivity type located in each base layer, each base layer constituting a portion of a respective unit cell region, a junction of each source layer within a corresponding base layer terminating at a surface thereof and at a distance from a junction between said corresponding base layer and the semiconductor layer;   a well layer of said first conductivity type located over the surface of second region of said semiconductor layer;   a gate electrode located in said first region such that said gate electrode overlaps at least a channel region with a gate insulating film interposed therebetween, said channel region being formed at a distance away from a surface of said base layer located between said semiconductor layer and said source layer, said gate electrode also being located over a surface of said second region with an insulating film interposed therebetween such that plural extensions of said gate electrode, of a predetermined length, extend in repetitive fashion from a side of said first region to a side of said second region along said border shared by said second region and said first region;   a source electrode having a first contact portion connected to the corresponding base layer and corresponding source layer in each of said unit cell regions, and a second contact portion connected to a contact region of said well layer;   a minority carrier extracting layer of the first conductivity type located at a surface of said well layer, said minority carrier extracting layer overlapping said well layer and including said second contact portion, said minority carrier extracting layer having an impurity concentration higher than said well layer so as to permit a flowing out of minority carriers, which have flowed from said semiconductor substrate into said second region of said semiconductor layer, into said source electrode; and   a gate electrode pad having contact portions connected to said plural extensions of said gate electrode and disposed over said minority carrier extracting layer formed at the surface of said well layer.