Three input arithmetic logic unit forming the sum of a first Boolean combination of first, second and third inputs plus a second Boolean combination of first, second and third inputs

Abstract

A three input arithmetic logic unit (230) forms a mixed arithmetic and Boolean combination of three multibit input signals. The arithmetic logic unit (230) first forms a Boolean combination and then forms an arithmetic combination. The current instruction drives an instruction decoder (250, 245) that generates the functions signals F0-F7 which control the combination formed. The arithmetic logic unit (230) includes a first three input Boolean function generator (496) forming a Boolean combination F1(A,B,C), a second three input Boolean function generator (497) forming a Boolean combination F2(A,B,C), and an adder (495) forming the sum of the two Boolean combinations. The first Boolean combination F1(A,B,C) and the second Boolean combination F2(A,B,C) are independently selected from the set of all possible Boolean combinations of three multibit input signals A, B and C. The adder (495) includes a least significant bit carry-in generator (246) supplying a carry input to the least significant bit. This carry input is determined by the combination being formed, and generally is "1" only during subtraction.

We claim: 
     
       1. A three input arithmetic logic unit comprising: a first three input Boolean function generator having a first input receiving a first multibit input signal A, a second input receiving a second multibit input signal B, a third input receiving a third multibit input signal C, and an output forming a first selected Boolean combination F1(A,B,C) of signals received at said first, second and third inputs;   a second three input Boolean function generator having a first input receiving the first multibit input signal A, a second input receiving the second multibit input signal B, and a third input receiving the third multibit input signal C and an output forming a second selected Boolean combination F2(A,B,C) of signals received at said first, second and third inputs; and   an adder having a first input connected to said output of said first three input Boolean function generator, a second input connected to said output of said second three input Boolean function generator and an output forming the sum of signals received at said first and second inputs.   
     
     
       2. The three input arithmetic logic unit of claim 1, further comprising: a least significant bit carry-in generator connected to said adder supplying a carry input to a least significant bit of said adder.   
     
     
       3. The three input arithmetic logic unit of claim 1, wherein: said first three input Boolean function generator includes a function input responsive to a first function control signal, said first three input Boolean function generator capable of forming said first Boolean combination F1(A,B,C) as any combination of a set of all possible Boolean combinations of the first multibit input signal A, the second multibit input signal B and the third multibit input signal C corresponding to said first function control signal, said first Boolean combination F1(A,B,C) formed corresponding to said first function control signal; and   said second three input Boolean function generator includes a function input responsive to a second function control signal, said second three input Boolean function generator forming said second Boolean combination F2(A,B,C) as any combination of a set of all possible Boolean combinations of the first multibit input signal A, the second multibit input signal B and the third multibit input signal C corresponding to said second function control signal, said second Boolean combination F2(A,B,C) formed corresponding to said second function control signal, said second Boolean combination F2(A,B,C) specified by said second function control signal independently from said first Boolean combination F1(A,B,C) specified by said first function control signal.   
     
     
       4. A data processing system comprising: a data system bus transferring data and addresses;   a system memory connected to said data system bus, said system memory storing data and transferring data via said data system bus;   a data processor circuit connected to said data system bus, said data processor circuit including an arithmetic logic unit having a first three input Boolean function generator having a first input receiving a first multibit input signal A, a second input receiving a second multibit input signal B, a third input receiving a third multibit input signal C, and an output forming a first selected Boolean combination F1(A,B,C) of signals received at said first, second and third inputs;   a second three input Boolean function generator having a first input receiving the first multibit input signal A, a second input receiving the second multibit input signal B, and a third input receiving the third multibit input signal C and an output forming a second selected Boolean combination F2(A,B,C) of signals received at said first, second and third inputs; and   an adder having a first input connected to said output of said first three input Boolean function generator, a second input connected to said output of said second three input Boolean function generator and an output forming the sum of signals received at said first and second inputs.     
     
     
       5. The data processing system of claim 4, wherein: said data processor circuit further including a least significant bit carry-in generator connected to said adder supplying a carry input to a least significant bit of said adder.   
     
     
       6. The data processing system of claim 4, further comprising: a plurality of data memories connected to said data processor circuit,   an instruction memory supplying instructions to said data processor circuit, and   a transfer controller connected to said data system bus, each of said data memories and said instruction memory controlling data transfer between said system memory and said plurality of data memories and between said system memory and said instruction memory.   
     
     
       7. The data processing system of claim 6, further comprising: at least one additional data processor circuit identical to said data processor circuit,   a plurality of additional data memories connected to each additional data processor circuit,   an additional instruction memory supplying instructions to each additional data processor circuit, and   Wherein said transfer controller is further connected to each of said additional data memories and each said additional instruction memory, said transfer controller further including means for controlling data transfer between said system memory and said each of said additional data memories and between said system memory and each said additional instruction memory.   
     
     
       8. The data processing system of claim 7, wherein: said data processor circuit, said data memories, said instruction memory, each of said additional data processor circuits, each of said additional data memories, each additional instruction memory and said transfer controller are formed on a single integrated circuit.   
     
     
       9. The data processing system of claim 6, further comprising: a master data processor,   a plurality of master data memories connected to said master data processor,   at least one master instruction memory supplying instructions to said master data processor, and   wherein said transfer controller is further connected to each of said master data memories and each said master instruction memory, said transfer controller further including means for controlling data transfer between said system memory and said each of said master data memories and between said system memory and each said master instruction memory.   
     
     
       10. The data processing system of claim 9, wherein: said data processor circuit, said data memories, said instruction memory, said master data processor, each of said master data memories, each master instruction memory and said transfer controller are formed on a single integrated circuit.   
     
     
       11. The data processor system of claim 4, wherein: said system memory consists of an image memory storing image data in a plurality of pixels; and   said data processor system further comprising:   an image display unit connected to said image memory generating a visually perceivable output of an image consisting of a plurality of pixels stored in said image memory.   
     
     
       12. The data processor system of claim 11, further comprising: a palette forming a connection between said image memory and said image display unit, said palette transforming pixels recalled from said image memory into video signals driving said image display unit;   and wherein said data processor circuit further includes a frame controller connected to said palette controlling said palette transformation of pixels into video signals.     
     
     
       13. The data processor system of claim 4, wherein: said system memory consists of an image memory storing image data in a plurality of pixels; and   said data processor system further comprising:   a printer connected to said image memory generating a printed output of an image consisting of a plurality of pixels stored in said image memory.   
     
     
       14. The data processor system of claim 13, wherein: said printer consists of a color printer.   
     
     
       15. The data processor system of claim 13, further comprising: a printer controller forming a connection between said image memory and said printer, said printer controller transforming pixels recalled from said image memory into print signals driving said printer;   and wherein said data processor circuit further includes a frame controller connected to said print controller controlling said print controller transformation of pixels into print signals.     
     
     
       16. The data processor system of claim 4, wherein: said system memory consists of an image memory storing image data in a plurality of pixels; and   said data processor system further comprising:   an imaging device connected to said image memory generating an image signal input.   
     
     
       17. The data processor system of claim 16, further comprising: an image capture controller forming a connection between said imaging device and said image memory, said image capture controller transforming said image signal into pixels supplied for storage in said image memory; and wherein said data processor circuit further includes     a frame controller connected to said image capture controller controlling said image capture controller transformation of said image signal into pixels.   
     
     
       18. The data processor system of claim 4, further comprising: a modem connected to said data system bus and to a communications line.   
     
     
       19. The data processor system of claim 4, further comprising: a host processing system connected to said data system bus.   
     
     
       20. The data processor system of claim 19, further comprising: a host system bus connected to said host processing system transferring data and addresses; and   at least one host peripheral connected to said host system bus.   
     
     
       21. The data processing system of claim 4, wherein: said data processor circuit wherein said first three input Boolean function generator includes a function input responsive to a first function control signal, said first three input Boolean function generator capable of forming said first Boolean combination F1(A,B,C) as any combination of a set of all possible Boolean combinations of the first multibit input signal A, the second multibit input signal B and the third multibit input signal C corresponding to said first function control signal, said first Boolean combination F1(A,B,C) formed corresponding to said first function control signal, and   said second three input Boolean function generator includes a function input responsive to a second function control signal, said second three input Boolean function generator forming said second Boolean combination F2(A,B,C) as any combination of a set of all possible Boolean combinations of the first multibit input signal A, the second multibit input signal B and the third multibit input signal C corresponding to said second function control signal, said second Boolean combination F2(A,B,C) formed corresponding to said second function control signal, said second Boolean combination F2(A,B,C) specified by said second function control signal independently from said first Boolean combination F1(A,B,C) specified by said first function control signal.