Programmable digital signal processor using switchable unit-delays for optimal hardware allocation

Abstract

A novel switchable unit-delay has been developed for the efficient implementation of programmable digital finite impulse response filters and correlators. A p-tap consisting of this novel switchable unit-delay and a two-non-zero-digit partial product generator and adder have been implemented. The combination of several p-taps, made possible by the switchable unit-delay, allows for the efficient implementation of coefficients with more than two non-zero digits. In a straightforward implementation of a programmable finite impulse response filter, many tap "multipliers" would significantly waste valuable computational resources since all filter taps would need to accommodate "difficult" coefficient values (i.e., many non-zero digits), while for any specific transfer function, most filter taps would not require such extreme capabilities. The switchable unit-delay not only allows the programing of the number of taps and the specific tap-coefficient values, it provides the capability for programing the optimal allocation of hardware resources to each filter tap.

We claim: 
     
       1. A first digital filter tap element having a first predetermined number of digits for part of a filter having a plurality of such tap elements for digitally filtering an input digital signal according to an algorithm based upon a first filter coefficient having a second predetermined number of digits, the first tap element comprising: a coefficient multiplier having the first number of digits for multiplying at least a part of the input with a coefficient to form a product;   an adder responsive to the product of the multiplier and a second input providing as an output the sum of the product and the second input;   a delay element providing both a delayed and an undelayed signal coupled to one of the inputs to the multiplier or the output of the adder; and   means for selecting between the delayed and undelayed signal so that where the second number is greater than the first number, a second such tap element is combined with the first element to multiply the digital signal with the coefficient having the second number of digits.   
     
     
       2. The digital filter delay element of claim 1, wherein a register is coupled between the output of the coefficient multiplier and the input of the adder.   
     
     
       3. The digital filter delay element of claim 1, wherein the second tap element includes: a second coefficient multiplier coupled to the input to provide a second product;   a second adder responsive to the second product of the multiplier and a third input providing as an output the sum of the product and the third input;   a second delay element responsive to the output of the second adder;   a second terminal selectively responsive to the output of the second adder and the output of the second delay element, the second terminal being coupled to the second input of the first adder; and   means for selecting whether the second terminal is responsive to the output of the second adder or the output of the second delay element.   
     
     
       4. The filter element of claim 1, wherein the digits in the coefficient comprises one of a set of negative one and one. 
     
     
       5. The filter element of claim 1, wherein the coefficient multiplier comprises only shifting circuitry. 
     
     
       6. The filter element of claim 1, wherein the coefficient is a canonic signed digit representation. 
     
     
       7. The filter element of claim 6, wherein the coefficient is a canonic signed digit representation comprised only of negative ones and ones. 
     
     
       8. A computational element in a filter having a plurality of such elements for performing a computation on an input with a coefficient of not greater than a predetermined precision comprised of: a coefficient multiplier to provide a product comprised of a part of the coefficient and the input;   an adder providing a sum of a second quantity and the product;   an output element responsive to the sum comprised of one of a group consisting of a selectively bypassable delay and a selectively controlled single pole single throw switching element such that bypassing the delay increases the precision of the multiplier.   
     
     
       9. A digital signal processor comprising a plurality of computational elements of claim 8, and a register storing a control word, the computational elements being coupled to each other in response to the control word to perform one of scalar product, matrix operations, and filtering operations on the input. 
     
     
       10. A method for digitally filtering a digital input signal with a digital filter algorithm having coefficients, each coefficient having a predetermined number of digits, the method comprising: providing a plurality of separate coefficient multipliers, adders, switching elements and delay elements, with the adders and delay elements having inputs and outputs, with at least some of the coefficient multipliers having less than a predetermined precision and with the multipliers providing a product of the input signal and some coefficient digits at an output and the output of each coefficient multiplier being coupled to a switching element selecting between an input to one of the delay elements and to an input of one of the adders;   for each coefficient having a precision greater than the predetermined number of digits, coupling the multiplier to the input of an adder and the output of the adder to the input of another adder to form a combined coefficient multiplier having a precision greater than the number of digits in each such coefficient.