Message-oriented bank controller interface

Abstract

Disclosed is a message oriented interface for communication between a bank controller unit and peripheral devices, such as channel units, in digital loop transmission systems. At least four registers are used for each peripheral device. Two registers are utilized to transmit control signals, and two registers are for data transmission. An additional data register can hold the last byte read by the bank controller unit in the event of an error so the byte can be re-read. The last byte of each message, which is utilized for error detection, is the exclusive OR function of the corresponding bits in all the previous bytes of the message. A service request can be asserted by a peripheral device to the Bank Controller Unit when a control signal is present in one of the registers. Means are also provided for indicating when a register is busy.

We claim: 
     
       1. In a bank peripheral device for use in a digital loop transmission system, a circuit for transmitting and receiving digital streams including multiple-byte data messages and control signals over a bank controller link comprising a single data bus between the peripheral device and a bank controller in said loop wherein the data messages comprise a plurality of header bytes, a plurality of information bytes, a Stop byte and a Checksum byte, each byte including a number of bit positions, the Checksum byte comprising bits which are an exclusive OR function of all bits in the same bit position in the previous bytes of the data message, said circuit comprising: a first control circuit adapted for coupling to the data bus and for transmitting multiple-byte messages in a transmit mode and receiving multiple-byte messages in a receive mode such that the data messages and control signals are transmitted and received over the single data bus;   a first register electrically coupled to the first control circuit and adapted to receive a request to send signal, a start of message out signal, and an end of message signal from the data bus in the receive mode and receive a start of message in signal and a message acknowledgment signal in the transmit mode;   a second control circuit;   a second register electrically coupled to said second control circuit and adapted to transmit a clear to send signal and a message acknowledgment signal on the bus in the receive mode and to transmit a request to send signal in the transmit mode;   a third register electrically coupled to said first control circuit and adapted to receive a first multiple-byte data message a byte at a time which is part of a received digital stream from the bus subsequent to the sending of the clear to send signal and the receipt of the start of message out signal;   a fourth register electrically coupled to said second control circuit and adapted to transmit a second multiple-byte data message generated by the peripheral device as part of a transmitted digital stream a byte at a time onto the bus subsequent to the receipt of the start of message in signal;   the second and fourth registers also being adapted for connection to the single data bus through the first control circuit in order to be able to transmit the multiple-byte data messages and control signals as part of the transmitted digital stream on the bus.   
     
     
       2. The circuit according to claim 1 further comprising a fifth register electrically coupled to said second control circuit in order to store data transmitted by said fourth register and also coupled to said first control circuit in order to transmit said data in case of an error in transmitting the data from the fourth register. 
     
     
       3. A digital loop transmission system comprising: a Bank Controller Unit; and   a plurality of peripheral devices which communicate with said Bank Controller Unit by digital streams including control signals and multiple-byte data messages on a common data bus between the peripheral device and the bank controller which messages are received in a receive mode and transmitted in a transmit mode by the peripheral devices, the data messages comprising a plurality of header bytes, a plurality of information bytes, a Stop byte and a Checksum byte, each byte including a number of bit positions, the Checksum byte comprising bits which are an exclusive OR function of all bits in the same bit position in the previous bytes of the data message, each of said peripheral devices comprising:   a first control circuit coupled to the data bus and adapted for transmitting in the transmit mode and receiving in the receive mode the multiple-byte data messages such that the data messages and control signals are transmitted and received over the single data bus;   a first register electrically coupled to the first control circuit and adapted to receive a request to send signal from the data bus in the receive mode and receive a start of message in signal and a message acknowledgment signal in the transmit mode;   a second control circuit;   a second register electrically coupled to said second control circuit and adapted to transmit a clear to send signal and a message acknowledgment signal in the receive mode and to transmit a request to send signal in the transmit mode;   a third register electrically coupled to said first control circuit and adapted to receive a first multiple-byte data message a byte at a time which is part of a received digital stream from the bus subsequent to the sending of the clear to send signal and the receipt of the start of message out signal;   a fourth register electrically coupled to said second control circuit and adapted to transmit a second multiple-byte data message generated by the peripheral device as part of a transmitted digital stream a byte at a time onto the bus subsequent to the receipt of the start of message signal;   the second and fourth registers also being connected to the single data bus through the first control circuit in order to be able to transmit the multiple-byte data messages and control signals as part of the transmitted digital stream onto the bus.   
     
     
       4. The circuit according to claim 3 further comprising a fifth register connected to said second control circuit in order to store data messages transmitted by said fourth register and to transmit said data messages in case an error in transmitting the data from the fourth register is detected by the Bank Controller Unit. 
     
     
       5. The system according to claim 3 wherein the peripheral devices are channel units. 
     
     
       6. The system according to claim 3 wherein the data messages have a byte length within the range 10-65,535. 
     
     
       7. The system according to claim 3 further comprising conductive means coupled to each of the peripheral devices for asserting a service request to the Bank Controller Unit when an appropriate signal is in the second register. 
     
     
       8. The system according to claim 3 wherein the first control circuit includes means for sending to the Bank Controller Unit a predetermined two-bit signal indicating when one of the registers is busy.